Luwei/reduce fork

cmake/configuring_primitive_list.cmake

@@ -1,5 +1,5 @@
 #===============================================================================
-# Copyright 2021 Intel Corporation
+# Copyright 2021-2023 Intel Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -66,6 +66,21 @@ else()
 endif()
 message(STATUS "Enabled primitive GPU ISA: ${DNNL_ENABLE_PRIMITIVE_GPU_ISA}")
 
+if (ONEDNN_ENABLE_GEMM_KERNELS_ISA STREQUAL "ALL")
+    set(BUILD_GEMM_KERNELS_ALL TRUE)
+elseif (ONEDNN_ENABLE_GEMM_KERNELS_ISA STREQUAL "NONE")
+    set(BUILD_GEMM_KERNELS_NONE TRUE)
+else()
+    foreach(isa ${ONEDNN_ENABLE_GEMM_KERNELS_ISA})
+        string(TOUPPER ${isa} uisa)
+        if(NOT "${uisa}" MATCHES "^(SSE41|AVX2|AVX512)$")
+            message(FATAL_ERROR "Unsupported primitive CPU ISA: ${uisa}")
+        endif()
+        set(BUILD_GEMM_${uisa} TRUE)
+    endforeach()
+endif()
+message(STATUS "Enabled GeMM kernels ISA: ${ONEDNN_ENABLE_GEMM_KERNELS_ISA}")
+
 # When certain primitives or primitive ISA are switched off, some functions may
 # become unused which is expected. Switch off warning for unused functions in
 # such cases.

cmake/dnnl_compat.cmake

@@ -61,6 +61,8 @@ set(COMPAT_CACHE_STRING_VARS
     "LIBRARY_NAME"
     "ENABLE_WORKLOAD"
     "ENABLE_PRIMITIVE"
+    "ENABLE_PRIMITIVE_CPU_ISA"
+    "ENABLE_PRIMITIVE_GPU_ISA"
     "ARCH_OPT_FLAGS"
     "CPU_RUNTIME"
     "GPU_RUNTIME"

cmake/options.cmake

@@ -149,6 +149,16 @@ set(DNNL_ENABLE_PRIMITIVE_GPU_ISA "ALL" CACHE STRING
     - <ISA_NAME>;<ISA_NAME>;... Includes only selected ISA to be enabled.
       Possible values are: GEN9, GEN11, XELP, XEHP, XEHPG, XEHPC.")
 
+set(ONEDNN_ENABLE_GEMM_KERNELS_ISA "ALL" CACHE STRING
+    "Specifies an ISA set of GeMM kernels residing in x64/gemm folder to be
+    available at build time. Valid values:
+    - ALL (the default). Includes all ISA kernels to be enabled.
+    - NONE. Removes all kernels and interfaces.
+    - <ISA_NAME>. Enables all ISA up to ISA_NAME included.
+      Possible value are: SSE41, AVX2, AVX512. The linear order is
+      SSE41 < AVX2 < AVX512 < AMX (or ALL). It means that if user selects, e.g.
+      AVX2 ISA, SSE41 kernels will also present at build time.")
+
 # =============
 # Optimizations
 # =============

doc/build/build_options.md

@@ -24,6 +24,7 @@ oneDNN supports the following build-time options.
 | ONEDNN_ENABLE_PRIMITIVE         | **ALL**, PRIMITIVE_NAME                    | Specifies a set of functionality to be available based on primitives                            |
 | ONEDNN_ENABLE_PRIMITIVE_CPU_ISA | **ALL**, CPU_ISA_NAME                      | Specifies a set of functionality to be available for CPU backend based on CPU ISA               |
 | ONEDNN_ENABLE_PRIMITIVE_GPU_ISA | **ALL**, GPU_ISA_NAME                      | Specifies a set of functionality to be available for GPU backend based on GPU ISA               |
+| ONEDNN_ENABLE_GEMM_KERNELS_ISA  | **ALL**, NONE, ISA_NAME                    | Specifies a set of functionality to be available for GeMM kernels for CPU backend based on ISA  |
 | ONEDNN_EXPERIMENTAL             | ON, **OFF**                                | Enables [experimental features](@ref dev_guide_experimental)                                    |
 | ONEDNN_VERBOSE                  | **ON**, OFF                                | Enables [verbose mode](@ref dev_guide_verbose)                                                  |
 | ONEDNN_AARCH64_USE_ACL          | ON, **OFF**                                | Enables integration with Arm Compute Library for AArch64 builds                                 |
@@ -109,6 +110,17 @@ always be available. Example that enables XeLP and XeHP set:
 -DONEDNN_ENABLE_PRIMITIVE_GPU_ISA=XELP;XEHP
 ```
 
+#### ONEDNN_ENABLE_GEMM_KERNELS_ISA
+This option supports several values: `ALL` (the default) which enables all
+ISA kernels from x64/gemm folder, `NONE` which disables all kernels and removes
+correspondent interfaces, or one of `SSE41`, `AVX2`, and `AVX512`. Values are
+linearly ordered as `SSE41` < `AVX2` < `AVX512`. When specified, selected ISA
+and all ISA that are "smaller" will be available. Example that leaves SSE41 and
+AVX2 sets, but removes AVX512 and AMX kernels:
+```
+-DONEDNN_ENABLE_GEMM_KERNELS_ISA=AVX2
+```
+
 ## CPU Options
 Intel Architecture Processors and compatible devices are supported by
 oneDNN CPU engine. The CPU engine is built by default but can be disabled

include/oneapi/dnnl/dnnl_config.h.in

@@ -193,4 +193,10 @@
 #cmakedefine01 BUILD_XEHP
 #cmakedefine01 BUILD_XEHPG
 #cmakedefine01 BUILD_XEHPC
+// GeMM kernels ISA controls
+#cmakedefine01 BUILD_GEMM_KERNELS_ALL
+#cmakedefine01 BUILD_GEMM_KERNELS_NONE
+#cmakedefine01 BUILD_GEMM_SSE41
+#cmakedefine01 BUILD_GEMM_AVX2
+#cmakedefine01 BUILD_GEMM_AVX512
 #endif