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8370947: Mitigate Neoverse-N1 erratum 1542419 negative impact on GenZGC performance #28328
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👋 Welcome back eastigeevich! A progress list of the required criteria for merging this PR into |
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❗ This change is not yet ready to be integrated. |
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/contributor add xmas92 |
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@eastig Syntax:
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/contributor add aboldtch |
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@eastig |
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Hi @fisk @theRealAph @xmas92 @shipilev I created this draft PR based on @xmas92 work master...xmas92:jdk:deferred_icache_invalidation Alex wrote about his implementation in JDK-8370947:
I see his changes touch other backends. I tried to minimize changes and to avoid them in other backends. This PR does not cover all cases in ZGC at the moment. It can be done as soon as we agree with a proper way to fix. I'd like to hear your opinion which way we should choose:
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Arm Neoverse N1 erratum 1542419: "The core might fetch a stale instruction from memory which violates the ordering of instruction fetches". It is fixed in Neoverse N1 r4p1.
Neoverse-N1 implementations mitigate erratum 1542419 with a workaround:
tlbi vae3is, xzrdsb sytlbi vae3is, xzrinvalidates translations for all address spaces (global for address). It waits for all memory accesses using in-scope old translation information to complete before it is considered complete.As this workaround has significant overhead, Arm Neoverse N1 (MP050) Software Developer Errata Notice version 29.0 suggests:
"Since one TLB inner-shareable invalidation is enough to avoid this erratum, the number of injected TLB invalidations should be minimized in the trap handler to mitigate the performance impact due to this workaround."
This PR introduces a mechanism to defer instruction cache (ICache) invalidation for AArch64 to address the Arm Neoverse N1 erratum 1542419, which causes significant performance overhead if ICache invalidation is performed too frequently. The implementation includes detection of affected Neoverse N1 CPUs and automatic enabling of the workaround for relevant Neoverse N1 revisions.
Changes include:
NeoverseN1Errata1542419to enable or disable the workaround for the erratum. The flag is automatically enabled for Neoverse N1 CPUs prior to r4p1, as detected during VM initialization.ICacheInvalidationContextclass to manage deferred ICache invalidation, with platform-specific logic for AArch64. This context is used to batch ICache invalidations, reducing performance impact. As the address for icache invalidation is not relevant, we use the nmethod's code start address.ICacheInvalidationContexton platforms where the workaround is not needed, ensuring portability and minimal impact on other architectures.ZBarrierSetAssembler,ZNMethod,RelocIterator, and related code) to accept adefer_icache_invalidationparameter, allowing ICache invalidation to be deferred and later performed in bulk.Progress
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gitCheckout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/28328/head:pull/28328$ git checkout pull/28328Update a local copy of the PR:
$ git checkout pull/28328$ git pull https://git.openjdk.org/jdk.git pull/28328/headUsing Skara CLI tools
Checkout this PR locally:
$ git pr checkout 28328View PR using the GUI difftool:
$ git pr show -t 28328Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/28328.diff