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Generalize [hard_float_reg_gen] to cover int_hard_reg
and avoid magic constants: [hard_reg_gen]
1 parent c2d3de7 commit 4ff71ae

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+16
-15
lines changed

1 file changed

+16
-15
lines changed

backend/arm64/proc.ml

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,8 @@ let float32_reg_name =
6767

6868
let num_register_classes = 2
6969

70-
let register_class r =
71-
match (r.typ : Cmm.machtype_component) with
70+
let register_class_of_machtype_component typ =
71+
match (typ : Cmm.machtype_component) with
7272
| Val | Int | Addr -> 0
7373
| Vec128 ->
7474
(* CR mslater: (SIMD) arm64 *)
@@ -78,6 +78,9 @@ let register_class r =
7878
fatal_error "arm64: got valx2 register"
7979
| Float | Float32 -> 1
8080

81+
let register_class r =
82+
register_class_of_machtype_component r.typ
83+
8184
let num_stack_slot_classes = 2
8285

8386
let stack_slot_class typ =
@@ -134,22 +137,20 @@ let register_name ty r =
134137

135138
(* Representation of hard registers by pseudo-registers *)
136139

137-
let hard_int_reg =
138-
let v = Array.make 28 Reg.dummy in
139-
for i = 0 to 27 do
140-
v.(i) <- Reg.at_location Int (Reg i)
141-
done;
142-
v
143140

144-
let hard_float_reg_gen kind =
145-
let v = Array.make 32 Reg.dummy in
146-
for i = 0 to 31 do
147-
v.(i) <- Reg.at_location kind (Reg(100 + i))
141+
let hard_reg_gen typ =
142+
let reg_class = register_class_of_machtype_component typ in
143+
let n = num_available_registers.(reg_class) in
144+
let first = first_available_register.(reg_class) in
145+
let v = Array.make n Reg.dummy in
146+
for i = 0 to n - 1 do
147+
v.(i) <- Reg.at_location typ (Reg(first + i))
148148
done;
149-
v
149+
v
150150

151-
let hard_float_reg = hard_float_reg_gen Float
152-
let hard_float32_reg = hard_float_reg_gen Float32
151+
let hard_int_reg = hard_reg_gen Int
152+
let hard_float_reg = hard_reg_gen Float
153+
let hard_float32_reg = hard_reg_gen Float32
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let all_phys_regs =
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Array.concat [hard_int_reg; hard_float_reg; hard_float32_reg; ]
155156

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