Added interrupt driven UARTE (open for feedback, do not merge yet)

Cargo.toml

@@ -11,6 +11,7 @@ members = [
   "nrf52840-hal",
   "nrf9160-hal",
   "examples/rtfm-demo",
+  "examples/rtfm-uarte-interrupts",
   "examples/spi-demo",
   "examples/twi-ssd1306",
 ]

examples/rtfm-demo/Cargo.toml

@@ -5,7 +5,7 @@ authors = ["James Munns <[email protected]>"]
 edition = "2018"
 
 [dependencies]
-cortex-m-rtfm = "0.4.3"
+cortex-m-rtfm = "0.4"
 panic-semihosting = "0.5.1"
 cortex-m-semihosting = "0.3.3"
 

examples/rtfm-uarte-interrupts/.cargo/config

@@ -0,0 +1,5 @@
+[target.thumbv7em-none-eabihf]
+runner = "arm-none-eabi-gdb -tui"
+
+[build]
+target = "thumbv7em-none-eabihf"

examples/rtfm-uarte-interrupts/.gdbinit

@@ -0,0 +1,10 @@
+set remotetimeout 60000
+target remote :2331
+set arm force-mode thumb
+
+# Uncomment to enable semihosting, when necessary
+monitor semihosting enable
+
+layout split
+monitor reset
+load

examples/rtfm-uarte-interrupts/Cargo.toml

@@ -0,0 +1,36 @@
+[package]
+name = "rtfm-uarte-interrupts"
+version = "0.1.0"
+authors = ["Per Lindgren <[email protected]>",
+           "Emil Fresk <[email protected]>"]
+edition = "2018"
+
+[dependencies]
+cortex-m-rtfm = "0.4"
+panic-semihosting = "0.5.1"
+cortex-m-semihosting = "0.3.3"
+heapless = ">= 0.5.0"
+
+[dependencies.nrf52810-hal]
+version = "0.8.0"
+path = "../../nrf52810-hal"
+optional = true
+features = ["UARTE_DMA_SIZE_16"]
+
+[dependencies.nrf52832-hal]
+version = "0.8.0"
+path = "../../nrf52832-hal"
+optional = true
+features = ["xxAB-package", "UARTE_DMA_SIZE_16"]
+
+[dependencies.nrf52840-hal]
+version = "0.8.0"
+path = "../../nrf52840-hal"
+optional = true
+features = ["UARTE_DMA_SIZE_16"]
+
+[features]
+52810 = ["nrf52810-hal"]
+52832 = ["nrf52832-hal"]
+52840 = ["nrf52840-hal"]
+default = ["52832"]

examples/rtfm-uarte-interrupts/src/main.rs

@@ -0,0 +1,138 @@
+#![no_main]
+#![no_std]
+
+// panic handler
+extern crate panic_semihosting;
+
+use cortex_m_semihosting::hprintln;
+
+#[cfg(feature = "52810")]
+use nrf52810_hal as hal;
+
+#[cfg(feature = "52832")]
+use nrf52832_hal as hal;
+
+#[cfg(feature = "52840")]
+use nrf52840_hal as hal;
+
+use hal::gpio::{p0, Level};
+use hal::target::{interrupt, TIMER0 as TIM0, UARTE0};
+use hal::timer::*;
+use hal::{
+    uarte::{
+        self,
+        interrupt_driven::{RXError, UarteDMAPool, UarteDMAPoolNode, UarteRX, UarteTX},
+    },
+    Uarte,
+};
+
+use heapless::{
+    consts,
+    pool::singleton::Box,
+    spsc::{Producer, Queue},
+};
+
+// Needed for the write! example code
+// use core::fmt::Write;
+// use heapless::pool::singleton::Pool;
+
+use rtfm::app;
+
+const NR_PACKAGES: usize = 10;
+const DMA_MEM: usize = core::mem::size_of::<UarteDMAPoolNode>() * NR_PACKAGES;
+
+// Using power-of-2 constants is faster (see the crate heapless for details)
+type TXQSize = consts::U4;
+
+#[app(device = crate::hal::target)]
+const APP: () = {
+    static mut RX: UarteRX<UARTE0, TIM0> = ();
+    static mut TX: UarteTX<UARTE0, TXQSize> = ();
+    static mut PRODUCER: Producer<'static, Box<UarteDMAPool>, TXQSize> = ();
+
+    #[init(spawn = [])]
+    fn init() -> init::LateResources {
+        // for the actual DMA buffers
+        static mut MEMORY: [u8; DMA_MEM] = [0; DMA_MEM];
+        // for the producer/consumer of TX
+        static mut TX_RB: Queue<Box<UarteDMAPool>, TXQSize> = Queue(heapless::i::Queue::new());
+
+        hprintln!("init").unwrap();
+
+        let port0 = p0::Parts::new(device.P0);
+
+        let uarte0 = Uarte::new(
+            device.UARTE0,
+            uarte::Pins {
+                // adafruit-nrf52-bluefruit-le, adafruit_nrf52pro, nRF52-DK, nRF52840-DK
+                txd: port0.p0_06.into_push_pull_output(Level::High).degrade(),
+                rxd: port0.p0_08.into_floating_input().degrade(),
+                // Use the following for DWM-1001 dev board
+                // txd: port0.p0_05.into_push_pull_output(Level::High).degrade(),
+                // rxd: port0.p0_11.into_floating_input().degrade(),
+                cts: None,
+                rts: None,
+            },
+            uarte::Parity::EXCLUDED,
+            uarte::Baudrate::BAUD115200,
+        );
+
+        let timer = Timer::new(device.TIMER0);
+        let (txp, txc) = TX_RB.split();
+        let (rx, tx) = uarte0.into_interrupt_driven(txc, timer, MEMORY);
+
+        init::LateResources {
+            RX: rx,
+            TX: tx,
+            PRODUCER: txp,
+        }
+    }
+
+    // // we can get Box<P> us being now the owner
+    #[task(capacity = 2, resources = [PRODUCER])]
+    fn printer(data: Box<UarteDMAPool>) {
+        // enqueue a test message
+        // let mut node = UarteDMAPool::alloc().unwrap().init(UarteDMAPoolNode::new());
+        // write!(&mut node, "test").unwrap(); // Using the write! trait
+        // node.write_slice(&b"test"[..]); // Using raw slice writing
+        // resources.PRODUCER.enqueue(node).unwrap();
+        // hprintln!("{:?}", &data).unwrap();
+
+        // Echo the buffer back without any changes or copying
+        resources.PRODUCER.enqueue(data).unwrap();
+        rtfm::pend(interrupt::UARTE0_UART0);
+    }
+
+    #[task]
+    fn rx_error(err: RXError) {
+        hprintln!("rx_error {:?}", err).unwrap();
+    }
+
+    #[interrupt(priority = 2, resources = [RX])]
+    fn TIMER0() {
+        resources.RX.process_timeout_interrupt();
+    }
+
+    #[interrupt(priority = 2, resources = [RX, TX], spawn = [printer, rx_error])]
+    fn UARTE0_UART0() {
+        // probe RX
+        match resources.RX.process_interrupt() {
+            Ok(Some(b)) => {
+                // delegate data to printer
+                match spawn.printer(b) {
+                    Err(_) => spawn.rx_error(RXError::OOM).unwrap(),
+                    _ => (),
+                };
+            }
+            Ok(None) => (), // no
+            Err(err) => spawn.rx_error(err).unwrap(),
+        }
+
+        resources.TX.process_interrupt();
+    }
+
+    extern "C" {
+        fn SWI1_EGU1();
+        fn SWI2_EGU2();
+    }
+};

nrf52-hal-common/Cargo.toml

@@ -22,6 +22,9 @@ nb = "0.1.1"
 fpa = "0.1.0"
 rand_core = "0.4.0"
 
+[dependencies.heapless]
+version = "0.5.1"
+
 [dependencies.void]
 default-features = false
 version = "1.0.2"
@@ -58,3 +61,10 @@ default = ["52832"]
 52832 = ["nrf52832-pac"]
 52840 = ["nrf52840-pac"]
 9160 = ["nrf9160-pac"]
+UARTE_DMA_SIZE_4 = []
+UARTE_DMA_SIZE_8 = []
+UARTE_DMA_SIZE_16 = []
+UARTE_DMA_SIZE_32 = []
+UARTE_DMA_SIZE_64 = []
+UARTE_DMA_SIZE_128 = []
+UARTE_DMA_SIZE_255 = []

nrf52-hal-common/src/lib.rs

@@ -17,12 +17,12 @@ pub use nrf9160_pac as target;
 pub mod clocks;
 pub mod delay;
 pub mod gpio;
-#[cfg(not(feature="9160"))]
+#[cfg(not(feature = "9160"))]
 pub mod rng;
 pub mod rtc;
 pub mod saadc;
 pub mod spim;
-#[cfg(not(feature="9160"))]
+#[cfg(not(feature = "9160"))]
 pub mod temp;
 pub mod time;
 pub mod timer;
@@ -46,7 +46,7 @@ pub mod target_constants {
     pub const SRAM_UPPER: usize = 0x3000_0000;
     pub const FORCE_COPY_BUFFER_SIZE: usize = 255;
 }
-#[cfg(any(feature = "52840", feature="9160"))]
+#[cfg(any(feature = "52840", feature = "9160"))]
 pub mod target_constants {
     // NRF52840 and NRF9160 16 bits 1..0xFFFF
     pub const EASY_DMA_SIZE: usize = 65535;
@@ -59,8 +59,7 @@ pub mod target_constants {
 /// Does this slice reside entirely within RAM?
 pub(crate) fn slice_in_ram(slice: &[u8]) -> bool {
     let ptr = slice.as_ptr() as usize;
-    ptr >= target_constants::SRAM_LOWER &&
-        (ptr + slice.len()) < target_constants::SRAM_UPPER
+    ptr >= target_constants::SRAM_LOWER && (ptr + slice.len()) < target_constants::SRAM_UPPER
 }
 
 /// A handy structure for converting rust slices into ptr and len pairs
@@ -73,10 +72,7 @@ pub(crate) struct DmaSlice {
 
 impl DmaSlice {
     pub fn null() -> Self {
-        Self {
-            ptr: 0,
-            len: 0,
-        }
+        Self { ptr: 0, len: 0 }
     }
 
     pub fn from_slice(slice: &[u8]) -> Self {
@@ -89,7 +85,7 @@ impl DmaSlice {
 
 pub use crate::clocks::Clocks;
 pub use crate::delay::Delay;
-#[cfg(not(feature="9160"))]
+#[cfg(not(feature = "9160"))]
 pub use crate::rng::Rng;
 pub use crate::rtc::Rtc;
 pub use crate::saadc::Saadc;

nrf52-hal-common/src/timer.rs

@@ -22,7 +22,6 @@ use core::marker::PhantomData;
 pub struct OneShot;
 pub struct Periodic;
 
-
 /// Interface to a TIMER instance
 ///
 /// Right now, this is a very basic interface. The timer will always be
@@ -105,6 +104,19 @@ where
         self.0.cc[1].read().bits()
     }
 
+    /// Clears the interrupt for this timer, external NVIC modification
+    ///
+    /// Enables an interrupt that is fired when the timer reaches the value that
+    /// is given as an argument to `start`.
+    pub(crate) fn clear_interrupt(&mut self) {
+        // As of this writing, the timer code only uses
+        // `cc[0]`/`events_compare[0]`. If the code is extended to use other
+        // compare registers, the following needs to be adapted.
+
+        // Reset the event, otherwise it will always read `1` from now on.
+        self.0.events_compare[0].write(|w| w);
+    }
+
     /// Enables the interrupt for this timer
     ///
     /// Enables an interrupt that is fired when the timer reaches the value that