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mips support #20

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merged 6 commits into from
Feb 22, 2024
Merged

mips support #20

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52fda1c
Update ruapu.h
nihui Feb 22, 2024
ff910e5
Update main.c
nihui Feb 22, 2024
2f5d935
Update README.md
nihui Feb 22, 2024
e07251c
Update ci-qemu.yml
nihui Feb 22, 2024
de41903
Update ci-qemu.yml
nihui Feb 22, 2024
1b0f329
Update ci-qemu.yml
nihui Feb 22, 2024
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4 changes: 2 additions & 2 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
Detect CPU ISA features with single-file

<table>
<tr><td>CPU</td><td>&#9989; x86, x86-64<br/>&#9989; arm, aarch64<br/>&#9989; risc-v</td><td rowspan=3>
<tr><td>CPU</td><td>&#9989; x86, x86-64<br/>&#9989; arm, aarch64<br/>&#9989; mips<br/>&#9989; risc-v</td><td rowspan=3>

```c
#define RUAPU_IMPLEMENTATION
Expand Down Expand Up @@ -220,7 +220,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
|x86|`mmx` `sse` `sse2` `sse3` `ssse3` `sse41` `sse42` `sse4a` `xop` `avx` `f16c` `fma` `fma4` `avx2` `avx512f` `avx512bw` `avx512cd` `avx512dq` `avx512vl` `avx512vnni` `avx512bf16` `avx512ifma` `avx512vbmi` `avx512vbmi2` `avx512fp16` `avxvnni` `avxvnniint8` `avxifma`|
|arm|`edsp` `neon` `vfpv4`|
|aarch64|`neon` `vfpv4` `cpuid` `asimdhp` `asimddp` `asimdfhm` `bf16` `i8mm` `sve` `sve2` `svebf16` `svei8mm` `svef32mm`|
|mips||
|mips|`msa`|
|powerpc||
|loongarch||
|risc-v|`i` `m` `a` `f` `d` `c`|
Expand Down
3 changes: 3 additions & 0 deletions main.c
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Expand Up @@ -65,6 +65,9 @@ int main()
PRINT_ISA_SUPPORT(neon)
PRINT_ISA_SUPPORT(vfpv4)

#elif __mips__
PRINT_ISA_SUPPORT(msa)

#elif __riscv
PRINT_ISA_SUPPORT(i)
PRINT_ISA_SUPPORT(m)
Expand Down
8 changes: 7 additions & 1 deletion ruapu.h
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Expand Up @@ -132,7 +132,7 @@ static int ruapu_detect_isa(ruapu_some_inst some_inst)

#if defined(__i386__) || defined(__x86_64__)
#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".byte " #__VA_ARGS__ : : : ); }
#elif __aarch64__ || __arm__ || __riscv
#elif __aarch64__ || __arm__ || __mips__ || __riscv
#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".word " #__VA_ARGS__ : : : ); }
#endif

Expand Down Expand Up @@ -211,6 +211,9 @@ RUAPU_INSTCODE(neon, 0xf2000d40) // vadd.f32 q0,q0,q0
RUAPU_INSTCODE(vfpv4, 0xf3b60600) // vcvt.f16.f32 d0,q0
#endif

#elif __mips__
RUAPU_INSTCODE(msa, 0x7900001b) // fmadd.w $w0,$w0,$w0

#elif __riscv
RUAPU_INSTCODE(i, 0x00a50533) // add a0,a0,a0
RUAPU_INSTCODE(m, 0x02a50533) // mul a0,a0,a0
Expand Down Expand Up @@ -277,6 +280,9 @@ RUAPU_ISAENTRY(edsp)
RUAPU_ISAENTRY(neon)
RUAPU_ISAENTRY(vfpv4)

#elif __mips__
RUAPU_ISAENTRY(msa)

#elif __riscv
RUAPU_ISAENTRY(i)
RUAPU_ISAENTRY(m)
Expand Down