detect risc-v vector extension

The RISC-V Vector Extension adds a vcsr CSR since version 0.8, which
does not appear in version 0.7.1. I confirmed this on Sipeed Lichee
Pi 4A, which has T-Head C910 cores inside, and the version of RVV is
0.7.1, Checking the existence of the vlenb CSR will be a way to
probe RVV but not v0p7.

For some concerns that some older kernels do not enable vector
support for userspace, this solution will also work to treat it as
the vector extension does not exist. This can be confirmed on T-Head
Vendor Kernel working on TH1520. As the RISC-V Vector Extension
Specification said: "Attempts to execute any vector instruction,
or to access the vector CSRs, raise an illegal-instruction exception
when mstatus.VS is set to Off."

Signed-off-by: Yangyu Chen <[email protected]>

README.md

@@ -69,7 +69,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
 |powerpc|`vsx`|
 |s390x|`zvector`|
 |loongarch|`lsx` `lasx`|
-|risc-v|`i` `m` `a` `f` `d` `c` `zba` `zbb` `zbc` `zbs` `zbkb` `zbkc` `zbkx` `zfa` `zfbfmin` `zfh` `zfhmin` `zicond` `zicsr` `zifencei` `zmmul` `xtheadba` `xtheadbb` `xtheadbs` `xtheadcondmov` `xtheadfmemidx` `xtheadfmv` `xtheadmac` `xtheadmemidx` `xtheadmempair` `xtheadsync` `xtheadvdot`|
+|risc-v|`i` `m` `a` `f` `d` `c` `v` `zba` `zbb` `zbc` `zbs` `zbkb` `zbkc` `zbkx` `zfa` `zfbfmin` `zfh` `zfhmin` `zicond` `zicsr` `zifencei` `zmmul` `xtheadba` `xtheadbb` `xtheadbs` `xtheadcondmov` `xtheadfmemidx` `xtheadfmv` `xtheadmac` `xtheadmemidx` `xtheadmempair` `xtheadsync` `xtheadvdot`|
 |openrisc| `orbis32` `orbis64` `orfpx32` `orfpx64` `orvdx64` |
 
 ## Let's ruapu

main.c

@@ -127,6 +127,7 @@ int main()
     PRINT_ISA_SUPPORT(f)
     PRINT_ISA_SUPPORT(d)
     PRINT_ISA_SUPPORT(c)
+    PRINT_ISA_SUPPORT(v)
     PRINT_ISA_SUPPORT(zba)
     PRINT_ISA_SUPPORT(zbb)
     PRINT_ISA_SUPPORT(zbc)

ruapu.h

@@ -306,6 +306,7 @@ RUAPU_INSTCODE(a, 0x100122af, 0x185122af) // lr.w t0,(sp) + sc.w t0,t0,(sp)
 RUAPU_INSTCODE(f, 0x10a57553) // fmul.s fa0,fa0,fa0
 RUAPU_INSTCODE(d, 0x12a57553) // fmul.d fa0,fa0,fa0
 RUAPU_INSTCODE(c, 0x0001952a) // add a0,a0,a0 + nop
+RUAPU_INSTCODE(v, 0x00f02573) // csrr a0,vcsr
 RUAPU_INSTCODE(zba, 0x20a52533) // sh1add a0,a0,a0
 RUAPU_INSTCODE(zbb, 0x40a57533) // andn a0,a0,a0
 RUAPU_INSTCODE(zbc, 0x0aa52533) // clmulr a0,a0,a0
@@ -461,6 +462,7 @@ RUAPU_ISAENTRY(a)
 RUAPU_ISAENTRY(f)
 RUAPU_ISAENTRY(d)
 RUAPU_ISAENTRY(c)
+RUAPU_ISAENTRY(v)
 RUAPU_ISAENTRY(zba)
 RUAPU_ISAENTRY(zbb)
 RUAPU_ISAENTRY(zbc)