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8 changes: 4 additions & 4 deletions .github/ISSUE_TEMPLATE/config.yml
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
blank_issues_enabled: false
contact_links:
- name: Bug
url: https://github.com/openhwgroup/cv32e40p/issues/new?template=bug.md
url: https://github.com/esl-epfl/cv32e40px/issues/new?template=bug.md
about: For bugs in the RTL, Documentation, Verification environment or Tool and Build system.
labels: "Type:Bug"
- name: Task
url: https://github.com/openhwgroup/cv32e40p/issues/new?template=task.md
url: https://github.com/esl-epfl/cv32e40px/issues/new?template=task.md
about: For any task except bug fixes.
labels: "Type:Task"
- name: Question
url: https://github.com/openhwgroup/cv32e40p/issues/new?template=question.md
url: https://github.com/esl-epfl/cv32e40px/issues/new?template=question.md
about: For general questions.
labels: "Type:Question"
- name: Enhancement
url: https://github.com/openhwgroup/cv32e40p/issues/new?template=enhancement.md
url: https://github.com/esl-epfl/cv32e40px/issues/new?template=enhancement.md
about: For feature requests and enhancements.
labels: "Type:Enhancement"
12 changes: 0 additions & 12 deletions .github/workflows/check_target_on_pr.yml

This file was deleted.

8 changes: 8 additions & 0 deletions .gitignore
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Expand Up @@ -18,3 +18,11 @@ TAGS
/build
/Bender.lock
/Bender.local
golden_reference_design
ref_design
golden.src
revised.src
cadence_conformal
synopsys_formality
questa_autocheck
reports
16 changes: 16 additions & 0 deletions CONTRIBUTING.md
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Expand Up @@ -7,6 +7,22 @@ The [OpenHW Work Flow](https://github.com/openhwgroup/core-v-docs/blob/master/ve
is required reading. You will find information about the implementation and usage of the CORE-V verification environments
in the [Verification Strategy](https://github.com/openhwgroup/core-v-docs/blob/master/verif/Common/OpenHWGroup_CORE-V_Verif_Strategy.pdf).

## Updating Copyright
The files in this repository are open-source artifacts licensed under the terms of the Solderpad license, see [LICENSE](LICENSE).
If you modify a file, a new copyright _may_ be added, but the existing copyright and license header _must not_ be removed or modified.
If your contribution uses a newer version of the existing license, you are encouraged to declare that with a one-liner SPDX header.

In the example below, a new copyright and updated license are added to an existing copyright and license:
```
// Copyright 2024 OpenHW Group and <member-company>
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License.
// ...remainder of original license header from ETHZ and UniBo.
```

## The Mechanics
1. From GitHub: [fork](https://help.github.com/articles/fork-a-repo/) the [cv32e40p](https://github.com/openhwgroup/cv32e40p) repository
2. Clone repository: `git clone https://github.com/[your_github_username]/cv32e40p`
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14 changes: 7 additions & 7 deletions README.md
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@@ -1,8 +1,8 @@
[![Build Status](https://travis-ci.com/pulp-platform/riscv.svg?branch=master)](https://travis-ci.com/pulp-platform/riscv)

# OpenHW Group CORE-V CV32E40P RISC-V IP
# OpenHW Group CORE-V CV32E40PX RISC-V IP

CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements
CV32E40PX is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements
the RV32IM\[F|Zfinx\]C instruction set architecture, and the PULP custom extensions for achieving
higher code density, performance, and energy efficiency \[[1](https://doi.org/10.1109/TVLSI.2017.2654506)\], \[[2](https://doi.org/10.1109/PATMOS.2017.8106976)\].
It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA.
Expand All @@ -14,12 +14,12 @@ when it has been contributed to [OpenHW Group](https://www.openhwgroup.org/).

## Documentation

The CV32E40P user manual can be found in the _docs_ folder and it is
The CV32E40PX user manual can be found in the _docs_ folder and it is
captured in reStructuredText, rendered to html using [Sphinx](https://docs.readthedocs.io/en/stable/intro/getting-started-with-sphinx.html).
These documents are viewable using readthedocs and can be viewed [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/).

## Verification
The verification environment for the CV32E40P is _not_ in this Repository. There is a small, simple testbench here which is
The verification environment for the CV32E40PX is _not_ in this Repository. There is a small, simple testbench here which is
useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master
branch of this repo.

Expand All @@ -31,7 +31,7 @@ The Makefiles supported in the **core-v-verif** project automatically clone the
## Changelog

A changelog is generated automatically in the documentation from the individual pull requests.
In order to enable automatic changelog generation within the CV32E40P documentation, the committer is required to label each pull request
In order to enable automatic changelog generation within the CV32E40PX documentation, the committer is required to label each pull request
that touches any file in 'rtl' (or any of its subdirectories) with *Component:RTL* and label each pull request that touches any file in
'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests that are not labeled or labeled with *ignore-for-release* are
ignored for the changelog generation.
Expand All @@ -40,7 +40,7 @@ Only the person who actually performs the merge can add these labels (you need c
1 label is applied and therefore pull requests that touches both RTL and documentation files in the same pull request are not allowed.

## Constraints
Example synthesis constraints for the CV32E40P are provided.
Example synthesis constraints for the CV32E40PX are provided.

## Contributing

Expand Down Expand Up @@ -71,7 +71,7 @@ Run `./util/format-verible` to format all the files.

## Issues and Troubleshooting

If you find any problems or issues with CV32E40P or the documentation, please check out the [issue
If you find any problems or issues with CV32E40PX or the documentation, please check out the [issue
tracker](https://github.com/openhwgroup/cv32e40p/issues) and create a new issue if your problem is
not yet tracked.

Expand Down
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