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use less type aliases (io is Lwt.t, buffer is Cstruct.t)
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hannesm committed May 22, 2024
1 parent 9ad448d commit bcd4a7b
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Showing 3 changed files with 16 additions and 30 deletions.
8 changes: 1 addition & 7 deletions src/vnetif-stack/vnetif_stack.ml
Original file line number Diff line number Diff line change
Expand Up @@ -19,15 +19,12 @@ open Lwt.Infix
module type Vnetif_stack =
sig
type backend
type buffer
type 'a io
type id
module V4V6 : Tcpip.Stack.V4V6
module Backend : Vnetif.BACKEND

(** Create a new IPv4 stack connected to an existing backend *)
val create_stack_ipv4 : cidr:Ipaddr.V4.Prefix.t ->
?gateway:Ipaddr.V4.t -> ?mtu:int -> ?monitor_fn:(buffer -> unit io) ->
?gateway:Ipaddr.V4.t -> ?mtu:int -> ?monitor_fn:(Cstruct.t -> unit Lwt.t) ->
?unlock_on_listen:Lwt_mutex.t ->
backend -> V4V6.t Lwt.t
end
Expand All @@ -36,9 +33,6 @@ module Vnetif_stack (B : Vnetif.BACKEND)(R : Mirage_random.S)(Time : Mirage_time
Vnetif_stack with type backend = B.t =
struct
type backend = B.t
type buffer = B.buffer
type 'a io = 'a B.io
type id = B.id

module Backend = B
module V = Vnetif.Make(Backend)
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20 changes: 8 additions & 12 deletions src/vnetif/vnetif.ml
Original file line number Diff line number Diff line change
Expand Up @@ -21,32 +21,28 @@ let src = Logs.Src.create "vnetif" ~doc:"in-memory network interface"
module Log = (val Logs.src_log src : Logs.LOG)

module type BACKEND = sig
type 'a io = 'a Lwt.t
type buffer = Cstruct.t
type id = int
type macaddr = Macaddr.t
type t

val register : t -> (id, Net.error) result
val unregister : t -> id -> unit io
val mac : t -> id -> macaddr
val write : t -> id -> size:int -> (buffer -> int) -> (unit, Net.error) result io
val set_listen_fn : t -> id -> (buffer -> unit io) -> unit
val unregister_and_flush : t -> id -> unit io
val register : t -> (int, Net.error) result
val unregister : t -> int -> unit Lwt.t
val mac : t -> int -> Macaddr.t
val write : t -> int -> size:int -> (Cstruct.t -> int) -> (unit, Net.error) result Lwt.t
val set_listen_fn : t -> int -> (Cstruct.t -> unit Lwt.t) -> unit
val unregister_and_flush : t -> int -> unit Lwt.t
end

module Make (B : BACKEND) = struct
type error = Net.error
let pp_error = Mirage_net.Net.pp_error

type t = {
id : B.id;
id : int;
backend : B.t;
mutable wake_on_disconnect : unit Lwt.u option; (* woken up when disconnect is called, used by listen *)
unlock_on_listen: Lwt_mutex.t option; (* unlocked when listen is called, used by tests *)
size_limit : int option;
stats : stats;
monitor_fn : (B.buffer -> unit Lwt.t) option;
monitor_fn : (Cstruct.t -> unit Lwt.t) option;
flush_on_disconnect : bool;
}

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18 changes: 7 additions & 11 deletions src/vnetif/vnetif.mli
Original file line number Diff line number Diff line change
Expand Up @@ -18,24 +18,20 @@
open Mirage_net

module type BACKEND = sig
type 'a io = 'a Lwt.t
type buffer = Cstruct.t
type id = int
type macaddr = Macaddr.t
type t

val register : t -> (id, Net.error) result
val unregister : t -> id -> unit io
val mac : t -> id -> macaddr
val write : t -> id -> size:int -> (buffer -> int) -> (unit, Net.error) result io
val set_listen_fn : t -> id -> (buffer -> unit io) -> unit
val unregister_and_flush : t -> id -> unit io
val register : t -> (int, Net.error) result
val unregister : t -> int -> unit Lwt.t
val mac : t -> int -> Macaddr.t
val write : t -> int -> size:int -> (Cstruct.t -> int) -> (unit, Net.error) result Lwt.t
val set_listen_fn : t -> int -> (Cstruct.t -> unit Lwt.t) -> unit
val unregister_and_flush : t -> int -> unit Lwt.t
end


(** Dummy interface for software bridge. *)
module Make(B : BACKEND) : sig
include Mirage_net.S
val connect : ?size_limit:int -> ?flush_on_disconnect:bool -> ?monitor_fn:(B.buffer -> unit Lwt.t) -> ?unlock_on_listen:Lwt_mutex.t -> B.t -> t Lwt.t
val connect : ?size_limit:int -> ?flush_on_disconnect:bool -> ?monitor_fn:(Cstruct.t -> unit Lwt.t) -> ?unlock_on_listen:Lwt_mutex.t -> B.t -> t Lwt.t
val disconnect : t -> unit Lwt.t
end

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