Move timer modules

Author: JalonWong

examples/f103c8/src/main.rs

@@ -11,7 +11,8 @@ use jw_stm32f1_hal as hal;
 use jw_stm32f1_hal::{
     Heap, Mcu,
     afio::{NONE_PIN, RemapDefault},
-    embedded_hal, embedded_io,
+    embedded_hal::{self, pwm::SetDutyCycle},
+    embedded_io,
     gpio::PinState,
     nvic_scb::PriorityGrouping,
     pac::{self, Interrupt},
@@ -70,8 +71,10 @@ fn main() -> ! {
     // let pin_rx = hal::afio::NONE_PIN;
 
     let config = uart::Config::default();
-    let uart1 = dp.USART1.constrain();
-    let (Some(uart_tx), Some(uart_rx)) = uart1.into_tx_rx((pin_tx, pin_rx), config, &mut mcu)
+    let (Some(uart_tx), Some(uart_rx)) =
+        dp.USART1
+            .constrain()
+            .into_tx_rx((pin_tx, pin_rx), config, &mut mcu)
     else {
         panic!()
     };
@@ -105,10 +108,10 @@ fn main() -> ! {
     else {
         panic!()
     };
-    bt.config_freq(1.MHz(), 20.kHz());
+    bt.config_freq(20.kHz());
 
     ch1.config(PwmMode::Mode1, PwmPolarity::ActiveHigh);
-    ch1.set_duty(ch1.get_max_duty() / 2);
+    ch1.set_duty_cycle(ch1.max_duty_cycle() / 2).ok();
 
     bt.start();
 

scripts/sync_code.py

@@ -15,9 +15,15 @@
     "src/timer/timer6.rs": "src/timer/timer1.rs",
     "src/timer/timer7.rs": "src/timer/timer6.rs",
     "src/timer/timer8.rs": "src/timer/timer1.rs",
-    "src/timer/timer15.rs": "src/timer/timer2.rs",
-    "src/timer/timer16.rs": "src/timer/timer2.rs",
-    "src/timer/timer17.rs": "src/timer/timer16.rs",
+    "src/timer/timer9.rs": "src/timer/timer1.rs",
+    "src/timer/timer10.rs": "src/timer/timer1.rs",
+    "src/timer/timer11.rs": "src/timer/timer10.rs",
+    "src/timer/timer12.rs": "src/timer/timer9.rs",
+    "src/timer/timer13.rs": "src/timer/timer10.rs",
+    "src/timer/timer14.rs": "src/timer/timer10.rs",
+    "src/timer/timer15.rs": "src/timer/timer9.rs",
+    "src/timer/timer16.rs": "src/timer/timer10.rs",
+    "src/timer/timer17.rs": "src/timer/timer10.rs",
 }
 BEGIN_PATTERN = re.compile(r"\/\/ sync .+\s")
 

src/common/timer/counter.rs

@@ -1,5 +1,6 @@
-use super::*;
-use fugit::{HertzU32 as Hertz, MicrosDurationU32};
+use super::{Error, Event, FTimer, GeneralTimer};
+use core::ops::{Deref, DerefMut};
+use fugit::{HertzU32 as Hertz, MicrosDurationU32, TimerDurationU32, TimerInstantU32};
 
 /// Hardware timers
 pub struct CounterHz<TIM> {
@@ -95,3 +96,101 @@ impl<TIM: GeneralTimer> CounterHz<TIM> {
         MicrosDurationU32::from_ticks(u32::try_from(1_000_000 * cnt / freq_divider).unwrap())
     }
 }
+
+// ----------------------------------------------------------------------------
+
+/// Periodic non-blocking timer that imlements [embedded_hal_02::timer::CountDown]
+pub struct Counter<TIM, const FREQ: u32>(pub(super) FTimer<TIM, FREQ>);
+
+impl<T, const FREQ: u32> Deref for Counter<T, FREQ> {
+    type Target = FTimer<T, FREQ>;
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+
+impl<T, const FREQ: u32> DerefMut for Counter<T, FREQ> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+
+/// `Counter` with precision of 1 μs (1 MHz sampling)
+pub type CounterUs<TIM> = Counter<TIM, 1_000_000>;
+
+/// `Counter` with precision of of 1 ms (1 kHz sampling)
+///
+/// NOTE: don't use this if your system frequency more than 65 MHz
+pub type CounterMs<TIM> = Counter<TIM, 1_000>;
+
+impl<TIM: GeneralTimer, const FREQ: u32> Counter<TIM, FREQ> {
+    /// Releases the TIM peripheral
+    pub fn release(mut self) -> FTimer<TIM, FREQ> {
+        // stop counter
+        self.tim.reset_config();
+        self.0
+    }
+
+    pub fn now(&self) -> TimerInstantU32<FREQ> {
+        TimerInstantU32::from_ticks(self.tim.read_count().into())
+    }
+
+    pub fn start(&mut self, timeout: TimerDurationU32<FREQ>) -> Result<(), Error> {
+        // pause
+        self.tim.disable_counter();
+
+        self.tim.clear_interrupt_flag(Event::Update);
+
+        // reset counter
+        self.tim.reset_counter();
+
+        self.tim.set_auto_reload(timeout.ticks() - 1)?;
+
+        // Trigger update event to load the registers
+        self.tim.trigger_update();
+
+        // start counter
+        self.tim.enable_counter();
+
+        Ok(())
+    }
+
+    pub fn wait(&mut self) -> nb::Result<(), Error> {
+        if self.tim.get_interrupt_flag().contains(Event::Update) {
+            self.tim.clear_interrupt_flag(Event::Update);
+            Ok(())
+        } else {
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
+    pub fn cancel(&mut self) -> Result<(), Error> {
+        if !self.tim.is_counter_enabled() {
+            return Err(Error::Disabled);
+        }
+
+        // disable counter
+        self.tim.disable_counter();
+        Ok(())
+    }
+}
+
+impl<TIM: GeneralTimer, const FREQ: u32> fugit_timer::Timer<FREQ> for Counter<TIM, FREQ> {
+    type Error = Error;
+
+    fn now(&mut self) -> TimerInstantU32<FREQ> {
+        Self::now(self)
+    }
+
+    fn start(&mut self, duration: TimerDurationU32<FREQ>) -> Result<(), Self::Error> {
+        self.start(duration)
+    }
+
+    fn cancel(&mut self) -> Result<(), Self::Error> {
+        self.cancel()
+    }
+
+    fn wait(&mut self) -> nb::Result<(), Self::Error> {
+        self.wait()
+    }
+}

src/timer/delay.rs src/common/timer/delay.rssrc/timer/delay.rs renamed to src/common/timer/delay.rs

@@ -75,3 +75,22 @@ impl<TIM: GeneralTimer, const FREQ: u32> fugit_timer::Delay<FREQ> for Delay<TIM,
         Ok(())
     }
 }
+
+// ----------------------------------------------------------------------------
+
+use embedded_hal::delay::DelayNs;
+use fugit::ExtU32Ceil;
+
+impl<TIM: GeneralTimer, const FREQ: u32> DelayNs for Delay<TIM, FREQ> {
+    fn delay_ns(&mut self, ns: u32) {
+        self.delay(ns.micros_at_least());
+    }
+
+    fn delay_us(&mut self, us: u32) {
+        self.delay(us.micros_at_least());
+    }
+
+    fn delay_ms(&mut self, ms: u32) {
+        self.delay(ms.millis_at_least());
+    }
+}

src/common/timer/fix_timer.rs

@@ -0,0 +1,78 @@
+use super::*;
+
+/// Timer wrapper for fixed precision timers.
+///
+/// Uses `fugit::TimerDurationU32` for most of operations
+pub struct FTimer<TIM, const FREQ: u32> {
+    pub(crate) tim: TIM,
+    clk: Hertz,
+}
+
+/// `FTimer` with precision of 1 μs (1 MHz sampling)
+pub type FTimerUs<TIM> = FTimer<TIM, 1_000_000>;
+
+/// `FTimer` with precision of 1 ms (1 kHz sampling)
+///
+/// NOTE: don't use this if your system frequency more than 65 MHz
+pub type FTimerMs<TIM> = FTimer<TIM, 1_000>;
+
+impl<TIM: GeneralTimer, const FREQ: u32> FTimer<TIM, FREQ> {
+    /// Initialize timer
+    pub fn new(tim: TIM, clk: Hertz) -> Self {
+        let mut t = Self { tim, clk };
+        t.configure();
+        t
+    }
+
+    /// Calculate prescaler depending on `Clocks` state
+    pub fn configure(&mut self) {
+        assert!(self.clk.raw() % FREQ == 0);
+        let psc = self.clk.raw() / FREQ;
+        self.tim.set_prescaler(u16::try_from(psc - 1).unwrap());
+    }
+
+    /// Creates `Counter` that imlements [embedded_hal_02::timer::CountDown]
+    pub fn counter(self) -> Counter<TIM, FREQ> {
+        Counter(self)
+    }
+
+    /// Creates `Delay` that imlements [embedded_hal_02::blocking::delay] traits
+    pub fn delay(self) -> Delay<TIM, FREQ> {
+        Delay(self)
+    }
+
+    /// Releases the TIM peripheral
+    pub fn release(self) -> TIM {
+        self.tim
+    }
+
+    /// Starts listening for an `event`
+    ///
+    /// Note, you will also have to enable the TIM2 interrupt in the NVIC to start
+    /// receiving events.
+    pub fn listen(&mut self, event: Event) {
+        self.tim.listen_interrupt(event, true);
+    }
+
+    /// Clears interrupt associated with `event`.
+    ///
+    /// If the interrupt is not cleared, it will immediately retrigger after
+    /// the ISR has finished.
+    pub fn clear_interrupt(&mut self, event: Event) {
+        self.tim.clear_interrupt_flag(event);
+    }
+
+    pub fn get_interrupt(&mut self) -> Event {
+        self.tim.get_interrupt_flag()
+    }
+
+    /// Stops listening for an `event`
+    pub fn unlisten(&mut self, event: Event) {
+        self.tim.listen_interrupt(event, false);
+    }
+
+    /// Stopping timer in debug mode can cause troubles when sampling the signal
+    pub fn stop_in_debug(&mut self, state: bool) {
+        self.tim.stop_in_debug(state);
+    }
+}

src/common/timer/mod.rs

@@ -2,23 +2,16 @@ pub mod pwm;
 pub use pwm::*;
 pub mod counter;
 pub use counter::*;
+pub mod fix_timer;
+pub use fix_timer::*;
+pub mod delay;
+pub use delay::*;
 
 use crate::time::Hertz;
 
-pub trait PwmTimer {
-    fn start(&mut self);
-    fn stop(&mut self);
-    fn config_freq(&mut self, count_freq: Hertz, update_freq: Hertz);
-    fn get_max_duty(&self) -> u32;
-    fn get_count_value(&self) -> u32;
-}
-
-pub trait PwmChannel {
+pub trait PwmChannel: embedded_hal::pwm::SetDutyCycle {
     fn config(&mut self, mode: PwmMode, polarity: PwmPolarity);
     fn set_enable(&mut self, en: bool);
-    fn get_max_duty(&self) -> u32;
-    /// Remember to use `get_max_duty()`
-    fn set_duty(&mut self, duty: u32);
 }
 
 // ----------------------------------------------------------------------------
@@ -37,6 +30,7 @@ pub trait GeneralTimer {
     fn read_prescaler(&self) -> u16;
     fn read_count(&self) -> u32;
     fn trigger_update(&mut self);
+    fn stop_in_debug(&mut self, state: bool);
     fn config_freq(&mut self, clock: Hertz, count_freq: Hertz, update_freq: Hertz);
 
     fn clear_interrupt_flag(&mut self, event: Event);
@@ -69,10 +63,13 @@ pub trait TimerWithPwm2Ch: TimerWithPwm1Ch {
     fn get_ch2_cc_value(&self) -> u32;
 }
 
-pub trait TimerWithPwm4Ch: TimerWithPwm2Ch {
+pub trait TimerWithPwm3Ch: TimerWithPwm2Ch {
     fn enable_ch3(&mut self, en: bool);
     fn set_ch3_cc_value(&mut self, value: u32);
     fn get_ch3_cc_value(&self) -> u32;
+}
+
+pub trait TimerWithPwm4Ch: TimerWithPwm3Ch {
     fn enable_ch4(&mut self, en: bool);
     fn set_ch4_cc_value(&mut self, value: u32);
     fn get_ch4_cc_value(&self) -> u32;