Improve timer modules

Author: JalonWong

src/common/timer.rs

@@ -0,0 +1,97 @@
+use super::*;
+use fugit::{HertzU32 as Hertz, MicrosDurationU32};
+
+/// Hardware timers
+pub struct CounterHz<TIM> {
+    pub(crate) tim: TIM,
+    pub(crate) clk: Hertz,
+}
+
+impl<TIM: GeneralTimer> CounterHz<TIM> {
+    pub fn start(&mut self, timeout: Hertz) -> Result<(), Error> {
+        // pause
+        self.tim.disable_counter();
+
+        self.tim.clear_interrupt_flag(Event::Update);
+
+        // reset counter
+        self.tim.reset_counter();
+
+        let clk = self.clk;
+        self.tim.config_freq(clk, clk, timeout);
+
+        // start counter
+        self.tim.enable_counter();
+
+        Ok(())
+    }
+
+    pub fn wait(&mut self) -> nb::Result<(), Error> {
+        if self.tim.get_interrupt_flag().contains(Event::Update) {
+            self.tim.clear_interrupt_flag(Event::Update);
+            Ok(())
+        } else {
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
+    pub fn cancel(&mut self) -> Result<(), Error> {
+        if !self.tim.is_counter_enabled() {
+            return Err(Error::Disabled);
+        }
+
+        // disable counter
+        self.tim.disable_counter();
+        Ok(())
+    }
+
+    /// Restarts the timer in count down mode with user-defined prescaler and auto-reload register
+    pub fn start_raw(&mut self, psc: u16, arr: u16) {
+        // pause
+        self.tim.disable_counter();
+
+        self.tim.set_prescaler(psc);
+
+        self.tim.set_auto_reload(arr as u32).unwrap();
+
+        // Trigger an update event to load the prescaler value to the clock
+        self.tim.trigger_update();
+
+        // start counter
+        self.tim.enable_counter();
+    }
+
+    /// Retrieves the content of the prescaler register. The real prescaler is this value + 1.
+    pub fn psc(&self) -> u16 {
+        self.tim.read_prescaler()
+    }
+
+    /// Retrieves the value of the auto-reload register.
+    pub fn arr(&self) -> u16 {
+        self.tim.read_auto_reload() as u16
+    }
+
+    /// Resets the counter
+    pub fn reset(&mut self) {
+        // Sets the URS bit to prevent an interrupt from being triggered by
+        // the UG bit
+        self.tim.trigger_update();
+    }
+
+    /// Returns the number of microseconds since the last update event.
+    /// *NOTE:* This method is not a very good candidate to keep track of time, because
+    /// it is very easy to lose an update event.
+    pub fn now(&self) -> MicrosDurationU32 {
+        let psc = self.tim.read_prescaler() as u32;
+
+        // freq_divider is always bigger than 0, since (psc + 1) is always less than
+        // timer_clock
+        let freq_divider = (self.clk.raw() / (psc + 1)) as u64;
+        let cnt: u32 = self.tim.read_count().into();
+        let cnt = cnt as u64;
+
+        // It is safe to make this cast, because the maximum timer period in this HAL is
+        // 1s (1Hz), then 1 second < (2^32 - 1) microseconds
+        MicrosDurationU32::from_ticks(u32::try_from(1_000_000 * cnt / freq_divider).unwrap())
+    }
+}

src/common/timer/counter.rs

@@ -0,0 +1,131 @@
+pub mod pwm;
+pub use pwm::*;
+pub mod counter;
+pub use counter::*;
+
+use crate::time::Hertz;
+
+pub trait PwmTimer {
+    fn start(&mut self);
+    fn stop(&mut self);
+    fn config_freq(&mut self, count_freq: Hertz, update_freq: Hertz);
+    fn get_max_duty(&self) -> u32;
+    fn get_count_value(&self) -> u32;
+}
+
+pub trait PwmChannel {
+    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity);
+    fn set_enable(&mut self, en: bool);
+    fn get_max_duty(&self) -> u32;
+    /// Remember to use `get_max_duty()`
+    fn set_duty(&mut self, duty: u32);
+}
+
+// ----------------------------------------------------------------------------
+
+pub trait GeneralTimer {
+    fn reset_config(&mut self);
+    fn enable_counter(&mut self);
+    fn disable_counter(&mut self);
+    fn is_counter_enabled(&self) -> bool;
+    fn reset_counter(&mut self);
+    fn max_auto_reload() -> u32;
+    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32);
+    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error>;
+    fn read_auto_reload(&self) -> u32;
+    fn set_prescaler(&mut self, psc: u16);
+    fn read_prescaler(&self) -> u16;
+    fn read_count(&self) -> u32;
+    fn trigger_update(&mut self);
+    fn config_freq(&mut self, clock: Hertz, count_freq: Hertz, update_freq: Hertz);
+
+    fn clear_interrupt_flag(&mut self, event: Event);
+    fn listen_interrupt(&mut self, event: Event, b: bool);
+    fn get_interrupt_flag(&self) -> Event;
+    fn start_one_pulse(&mut self);
+}
+
+pub trait TimerDirection: GeneralTimer {
+    fn set_count_direction(&mut self, dir: CountDirection);
+}
+
+pub trait TimerWithPwm: GeneralTimer {
+    fn start_pwm(&mut self);
+    fn stop_pwm(&mut self);
+
+    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode);
+    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity);
+}
+
+pub trait TimerWithPwm1Ch: TimerWithPwm {
+    fn enable_ch1(&mut self, en: bool);
+    fn set_ch1_cc_value(&mut self, value: u32);
+    fn get_ch1_cc_value(&self) -> u32;
+}
+
+pub trait TimerWithPwm2Ch: TimerWithPwm1Ch {
+    fn enable_ch2(&mut self, en: bool);
+    fn set_ch2_cc_value(&mut self, value: u32);
+    fn get_ch2_cc_value(&self) -> u32;
+}
+
+pub trait TimerWithPwm4Ch: TimerWithPwm2Ch {
+    fn enable_ch3(&mut self, en: bool);
+    fn set_ch3_cc_value(&mut self, value: u32);
+    fn get_ch3_cc_value(&self) -> u32;
+    fn enable_ch4(&mut self, en: bool);
+    fn set_ch4_cc_value(&mut self, value: u32);
+    fn get_ch4_cc_value(&self) -> u32;
+}
+
+// Enumerate ------------------------------------------------------------------
+
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub enum Channel {
+    C1,
+    C2,
+    C3,
+    C4,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum CountDirection {
+    Up,
+    Down,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum PwmMode {
+    Mode1,
+    Mode2,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum PwmPolarity {
+    ActiveHigh,
+    ActiveLow,
+}
+
+#[derive(Debug, Eq, PartialEq, Copy, Clone)]
+pub enum Error {
+    /// Timer is disabled
+    Disabled,
+    WrongAutoReload,
+}
+
+/// Interrupt events
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub enum SysEvent {
+    /// [Timer] timed out / count down ended
+    Update,
+}
+
+bitflags::bitflags! {
+    pub struct Event: u32 {
+        const Update  = 1 << 0;
+        const C1 = 1 << 1;
+        const C2 = 1 << 2;
+        const C3 = 1 << 3;
+        const C4 = 1 << 4;
+    }
+}

src/common/timer/mod.rs

@@ -0,0 +1,132 @@
+use super::*;
+use crate::timer::Channel;
+
+// Implement Traits -----------------------------------------------------------
+
+pub struct PwmChannel1<TIM> {
+    tim: TIM,
+}
+impl<TIM> PwmChannel1<TIM> {
+    pub fn new(tim: TIM) -> Self {
+        Self { tim }
+    }
+}
+impl<TIM: TimerWithPwm1Ch> PwmChannel for PwmChannel1<TIM> {
+    #[inline(always)]
+    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity) {
+        self.tim
+            .preload_output_channel_in_mode(Channel::C1, mode.into());
+        self.tim.set_polarity(Channel::C1, polarity);
+    }
+
+    #[inline(always)]
+    fn set_enable(&mut self, en: bool) {
+        self.tim.enable_ch1(en);
+    }
+
+    #[inline(always)]
+    fn get_max_duty(&self) -> u32 {
+        (self.tim.read_auto_reload() as u32).wrapping_add(1)
+    }
+
+    #[inline(always)]
+    fn set_duty(&mut self, duty: u32) {
+        self.tim.set_ch1_cc_value(duty);
+    }
+}
+
+pub struct PwmChannel2<TIM> {
+    pub(super) tim: TIM,
+}
+impl<TIM> PwmChannel2<TIM> {
+    pub fn new(tim: TIM) -> Self {
+        Self { tim }
+    }
+}
+impl<TIM: TimerWithPwm2Ch> PwmChannel for PwmChannel2<TIM> {
+    #[inline(always)]
+    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity) {
+        self.tim
+            .preload_output_channel_in_mode(Channel::C2, mode.into());
+        self.tim.set_polarity(Channel::C2, polarity);
+    }
+
+    #[inline(always)]
+    fn set_enable(&mut self, en: bool) {
+        self.tim.enable_ch2(en);
+    }
+
+    #[inline(always)]
+    fn get_max_duty(&self) -> u32 {
+        (self.tim.read_auto_reload() as u32).wrapping_add(1)
+    }
+
+    #[inline(always)]
+    fn set_duty(&mut self, duty: u32) {
+        self.tim.set_ch2_cc_value(duty);
+    }
+}
+
+pub struct PwmChannel3<TIM> {
+    pub(super) tim: TIM,
+}
+impl<TIM> PwmChannel3<TIM> {
+    pub fn new(tim: TIM) -> Self {
+        Self { tim }
+    }
+}
+impl<TIM: TimerWithPwm4Ch> PwmChannel for PwmChannel3<TIM> {
+    #[inline(always)]
+    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity) {
+        self.tim
+            .preload_output_channel_in_mode(Channel::C3, mode.into());
+        self.tim.set_polarity(Channel::C3, polarity);
+    }
+
+    #[inline(always)]
+    fn set_enable(&mut self, en: bool) {
+        self.tim.enable_ch3(en);
+    }
+
+    #[inline(always)]
+    fn get_max_duty(&self) -> u32 {
+        (self.tim.read_auto_reload() as u32).wrapping_add(1)
+    }
+
+    #[inline(always)]
+    fn set_duty(&mut self, duty: u32) {
+        self.tim.set_ch3_cc_value(duty);
+    }
+}
+
+pub struct PwmChannel4<TIM> {
+    pub(super) tim: TIM,
+}
+impl<TIM> PwmChannel4<TIM> {
+    pub fn new(tim: TIM) -> Self {
+        Self { tim }
+    }
+}
+impl<TIM: TimerWithPwm4Ch> PwmChannel for PwmChannel4<TIM> {
+    #[inline(always)]
+    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity) {
+        self.tim
+            .preload_output_channel_in_mode(Channel::C4, mode.into());
+        self.tim.set_polarity(Channel::C4, polarity);
+    }
+
+    #[inline(always)]
+    fn set_enable(&mut self, en: bool) {
+        self.tim.enable_ch4(en);
+    }
+
+    #[inline(always)]
+    fn get_max_duty(&self) -> u32 {
+        (self.tim.read_auto_reload() as u32).wrapping_add(1)
+    }
+
+    #[inline(always)]
+    fn set_duty(&mut self, duty: u32) {
+        self.tim.set_ch4_cc_value(duty);
+    }
+}