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two variants; debugger now runs on Core1
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,5 +1,5 @@ | ||
| <!DOCTYPE Board_Memory_Definition_File> | ||
| <Root name="Cortex-M0"> | ||
| <MemorySegment start="0x20030000" size="0x4100" access="Read/Write" name="SRAM" /> | ||
| <MemorySegment start="0x2003BF00" size="0x4100" access="Read/Write" name="SRAM" /> | ||
| <MemorySegment start="0x15000000" size="0x4000" access="Read/Write" name="XIP_SRAM" /> | ||
| </Root> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,15 @@ | ||
| <!DOCTYPE Linker_Placement_File> | ||
| <Root name="picodebug Section Placement"> | ||
| <MemorySegment name="SRAM"> | ||
| <ProgramSection alignment="4" load="Yes" name=".boot" /> | ||
| <ProgramSection alignment="4" load="Yes" name=".bootc" /> | ||
| <ProgramSection alignment="0x100" load="Yes" name=".vectors" /> | ||
| <ProgramSection alignment="4" load="Yes" name=".text" /> | ||
| <ProgramSection alignment="4" load="Yes" name=".data" /> | ||
| <ProgramSection alignment="4" load="Yes" name=".rodata" /> | ||
| <ProgramSection alignment="4" load="No" name=".bss" /> | ||
| <ProgramSection alignment="8" size="__STACKSIZE__" load="No" name=".stack" /> | ||
| </MemorySegment> | ||
| <MemorySegment name="XIP_SRAM"> | ||
| </MemorySegment> | ||
| </Root> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,58 @@ | ||
| /* | ||
| * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. | ||
| * | ||
| * SPDX-License-Identifier: BSD-3-Clause | ||
| */ | ||
|
|
||
| #include <rp2040.h> | ||
|
|
||
| static inline bool multicore_fifo_rvalid() { | ||
| return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS); | ||
| } | ||
|
|
||
| static inline void multicore_fifo_drain() { | ||
| while (multicore_fifo_rvalid()) | ||
| (void) sio_hw->fifo_rd; | ||
| } | ||
|
|
||
| static inline bool multicore_fifo_wready() { | ||
| return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS); | ||
| } | ||
|
|
||
| static inline void multicore_fifo_push_blocking(uint32_t data) { | ||
| // We wait for the fifo to have some space | ||
| while (!multicore_fifo_wready()) | ||
| tight_loop_contents(); | ||
|
|
||
| sio_hw->fifo_wr = data; | ||
|
|
||
| // Fire off an event to the other core | ||
| __SEV(); | ||
| } | ||
|
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| static inline uint32_t multicore_fifo_pop_blocking(void) { | ||
| // If nothing there yet, we wait for an event first, | ||
| // to try and avoid too much busy waiting | ||
| while (!multicore_fifo_rvalid()) | ||
| __WFE(); | ||
|
|
||
| return sio_hw->fifo_rd; | ||
| } | ||
|
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||
| __attribute__ (( section(".bootc") )) void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) { | ||
| uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry}; | ||
|
|
||
| uint seq = 0; | ||
| do { | ||
| uint cmd = cmd_sequence[seq]; | ||
| // we drain before sending a 0 | ||
| if (!cmd) { | ||
| multicore_fifo_drain(); | ||
| __SEV(); // core 1 may be waiting for fifo space | ||
| } | ||
| multicore_fifo_push_blocking(cmd); | ||
| uint32_t response = multicore_fifo_pop_blocking(); | ||
| // move to next state on correct response otherwise start over | ||
| seq = cmd == response ? seq + 1 : 0; | ||
| } while (seq < (sizeof(cmd_sequence) / sizeof(*cmd_sequence))); | ||
| } |
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