GitHub - louay-hesham/MultiCycleMIPS: Multicycle MIPS processor using SystemVerilog

Multicycle MIPS processor implementation using SystemVerilog

Name		Name	Last commit message	Last commit date
Latest commit History 54 Commits
.gitignore		.gitignore
MultiCycleMIPS.cr.mti		MultiCycleMIPS.cr.mti
MultiCycleMIPS.mpf		MultiCycleMIPS.mpf
README.md		README.md
alu.sv		alu.sv
aludecoder.sv		aludecoder.sv
controller.sv		controller.sv
datapath.sv		datapath.sv
dmem.sv		dmem.sv
flipflop.sv		flipflop.sv
leftshift.sv		leftshift.sv
maindecoder.sv		maindecoder.sv
memfile.dat		memfile.dat
mips.sv		mips.sv
multiplexer.sv		multiplexer.sv
mux4.sv		mux4.sv
regfile.sv		regfile.sv
signextention.sv		signextention.sv
testbench.sv		testbench.sv
top.sv		top.sv

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