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[RISCV] Remove -mattr=+no-rvc-hints #145138

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@topperc topperc commented Jun 21, 2025

As far as I know binutils does not have a similar option and I don't know of a reason we shouldn't accept the RVC hint instructions.

@topperc
[RISCV] Remove -mattr=+no-rvc-hints
9688f58 
As far as I know binutils does not have a similar option and I don't
know of a reason we shouldn't accept the RVC hint instructions.
@llvmbot llvmbot added backend:RISC-V mc Machine (object) code labels Jun 21, 2025
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llvmbot commented Jun 21, 2025

@llvm/pr-subscribers-mc

Author: Craig Topper (topperc)

Changes

As far as I know binutils does not have a similar option and I don't know of a reason we shouldn't accept the RVC hint instructions.

Full diff: https://github.com/llvm/llvm-project/pull/145138.diff

8 Files Affected:

  • (modified) llvm/docs/ReleaseNotes.md (+1)
  • (modified) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp (+1-1)
  • (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (-7)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+1-1)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+5-5)
  • (modified) llvm/test/CodeGen/RISCV/features-info.ll (-1)
  • (modified) llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt (-68)
  • (modified) llvm/test/MC/RISCV/rv32c-invalid.s (+2-9)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0395f43c61953..3713cc1e4161c 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -211,6 +211,7 @@ Changes to the RISC-V Backend
 * `-mcpu=sifive-x390` was added.
 * `-mtune=andes-45-series` was added.
 * Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
+* Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index d4d7de289a107..d12d033f878f9 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -292,7 +292,7 @@ void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
     NontemporalMode += 0b10;
 
   MCInst Hint;
-  if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
+  if (STI->hasStdExtCOrZca())
     Hint.setOpcode(RISCV::C_ADD_HINT);
   else
     Hint.setOpcode(RISCV::ADD);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6df6368929dac..224da07696fd0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -373,13 +373,6 @@ def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
 def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
 
 // Compressed Extensions
-def FeatureNoRVCHints
-    : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
-                       "Disable RVC Hint Instructions.">;
-def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
-                  AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
-                                     "RVC Hint Instructions">;
-
 def FeatureStdExtZca
     : RISCVExtension<1, 0,
                      "part of the C extension, excluding compressed "
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d9ef911b9a32e..bd6913362b516 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1717,7 +1717,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   if (!MI.memoperands_empty()) {
     MachineMemOperand *MMO = *(MI.memoperands_begin());
     if (STI.hasStdExtZihintntl() && MMO->isNonTemporal()) {
-      if (STI.hasStdExtCOrZca() && STI.enableRVCHintInstrs()) {
+      if (STI.hasStdExtCOrZca()) {
         if (isCompressibleInst(MI, STI))
           return 4; // c.ntl.all + c.load/c.store
         return 6;   // c.ntl.all + load/store
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index fd8591f5ab2d8..9c1db7ccef5ea 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -608,7 +608,7 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
 // HINT Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+let Predicates = [HasStdExtCOrZca], hasSideEffects = 0, mayLoad = 0,
     mayStore = 0 in {
 
 def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
@@ -691,24 +691,24 @@ def C_SRAI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
   let Inst{12} = 0;
 }
 
-} // Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+} // Predicates = [HasStdExtCOrZca], hasSideEffects = 0, mayLoad = 0,
   // mayStore = 0
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtCOrZca, HasRVCHints] in {
+let Predicates = [HasStdExtCOrZca] in {
 // Just a different syntax for the c.nop hint: c.addi x0, simm6 vs c.nop simm6.
 def : InstAlias<"c.addi x0, $imm", (C_NOP_HINT simm6nonzero:$imm), 0>;
 }
 
-let Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl] in {
+let Predicates = [HasStdExtC, HasStdExtZihintntl] in {
 def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
 def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
 def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
 def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
-} // Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl]
+} // Predicates = [HasStdExtC, HasStdExtZihintntl]
 
 let EmitPriority = 0 in {
 let Predicates = [HasStdExtCOrZca] in {
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 8b931f70aa5cc..999ecba7f1b9c 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -61,7 +61,6 @@
 ; CHECK-NEXT:   m                                - 'M' (Integer Multiplication and Division).
 ; CHECK-NEXT:   mips-p8700                       - MIPS p8700 processor.
 ; CHECK-NEXT:   no-default-unroll                - Disable default unroll preference..
-; CHECK-NEXT:   no-rvc-hints                     - Disable RVC Hint Instructions..
 ; CHECK-NEXT:   no-sink-splat-operands           - Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions.
 ; CHECK-NEXT:   no-trailing-seq-cst-fence        - Disable trailing fence for seq-cst store..
 ; CHECK-NEXT:   optimized-nf2-segment-load-store - vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle.
diff --git a/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt b/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt
index 17889c15cbf95..0a83a200c9317 100644
--- a/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt
+++ b/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt
@@ -10,265 +10,197 @@
 # RUN: llvm-mc --disassemble -triple=riscv32  -mattr=+c -mattr=+Zcmop \
 # RUN:     -M no-aliases --show-encoding < %s | \
 # RUN:   FileCheck --check-prefixes=GOOD,MOP %s
-#
-# RUN: llvm-mc --disassemble -triple=riscv32  -mattr=+c -mattr=+no-rvc-hints \
-# RUN:     -M no-aliases --show-encoding < %s 2>&1 | \
-# RUN:   FileCheck --check-prefix=NOHINTS %s
 
 # BAD: invalid instruction encoding
-# NOHINTS: invalid instruction encoding
 0x01 0x60
 
 # GOOD: c.lui zero, 1
-# NOHINTS: invalid instruction encoding
 0x05 0x60
 
 # GOOD: c.lui zero, 2
-# NOHINTS: invalid instruction encoding
 0x09 0x60
 
 # GOOD: c.lui zero, 3
-# NOHINTS: invalid instruction encoding
 0x0D 0x60
 
 # GOOD: c.lui zero, 4
-# NOHINTS: invalid instruction encoding
 0x11 0x060
 
 # GOOD: c.lui zero, 5
-# NOHINTS: invalid instruction encoding
 0x15 0x60
 
 # GOOD: c.lui zero, 6
-# NOHINTS: invalid instruction encoding
 0x19 0x60
 
 # GOOD: c.lui zero, 7
-# NOHINTS: invalid instruction encoding
 0x1D 0x60
 
 # GOOD: c.lui zero, 8
-# NOHINTS: invalid instruction encoding
 0x21 0x60
 
 # GOOD: c.lui zero, 9
-# NOHINTS: invalid instruction encoding
 0x25 0x60
 
 # GOOD: c.lui zero, 10
-# NOHINTS: invalid instruction encoding
 0x29 0x60
 
 # GOOD: c.lui zero, 11
-# NOHINTS: invalid instruction encoding
 0x2D 0x60
 
 # GOOD: c.lui zero, 12
-# NOHINTS: invalid instruction encoding
 0x31 0x60
 
 # GOOD: c.lui zero, 13
-# NOHINTS: invalid instruction encoding
 0x35 0x60
 
 # GOOD: c.lui zero, 14
-# NOHINTS: invalid instruction encoding
 0x39 0x60
 
 # GOOD: c.lui zero, 15
-# NOHINTS: invalid instruction encoding
 0x3D 0x60
 
 # GOOD: c.lui zero, 16
-# NOHINTS: invalid instruction encoding
 0x41 0x60
 
 # GOOD: c.lui zero, 17
-# NOHINTS: invalid instruction encoding
 0x45 0x60
 
 # GOOD: c.lui zero, 18
-# NOHINTS: invalid instruction encoding
 0x49 0x60
 
 # GOOD: c.lui zero, 19
-# NOHINTS: invalid instruction encoding
 0x4D 0x60
 
 # GOOD: c.lui zero, 20
-# NOHINTS: invalid instruction encoding
 0x51 0x60
 
 # GOOD: c.lui zero, 21
-# NOHINTS: invalid instruction encoding
 0x55 0x60
 
 # GOOD: c.lui zero, 22
-# NOHINTS: invalid instruction encoding
 0x59 0x60
 
 # GOOD: c.lui zero, 23
-# NOHINTS: invalid instruction encoding
 0x5D 0x60
 
 # GOOD: c.lui zero, 24
-# NOHINTS: invalid instruction encoding
 0x61 0x60
 
 # GOOD: c.lui zero, 25
-# NOHINTS: invalid instruction encoding
 0x65 0x60
 
 # GOOD: c.lui zero, 26
-# NOHINTS: invalid instruction encoding
 0x69 0x60
 
 # GOOD: c.lui zero, 27
-# NOHINTS: invalid instruction encoding
 0x6D 0x60
 
 # GOOD: c.lui zero, 28
-# NOHINTS: invalid instruction encoding
 0x71 0x60
 
 # GOOD: c.lui zero, 29
-# NOHINTS: invalid instruction encoding
 0x75 0x60
 
 # GOOD: c.lui zero, 30
-# NOHINTS: invalid instruction encoding
 0x79 0x60
 
 # GOOD: c.lui zero, 31
-# NOHINTS: invalid instruction encoding
 0x7D 0x60
 
 # GOOD: c.lui zero, 1048544
-# NOHINTS: invalid instruction encoding
 0x01 0x70
 
 # GOOD: c.lui zero, 1048545
-# NOHINTS: invalid instruction encoding
 0x05 0x70
 
 # GOOD: c.lui zero, 1048546
-# NOHINTS: invalid instruction encoding
 0x09 0x70
 
 # GOOD: c.lui zero, 1048547
-# NOHINTS: invalid instruction encoding
 0x0D 0x70
 
 # GOOD: c.lui zero, 1048548
-# NOHINTS: invalid instruction encoding
 0x11 0x70
 
 # GOOD: c.lui zero, 1048549
-# NOHINTS: invalid instruction encoding
 0x15 0x70
 
 # GOOD: c.lui zero, 1048550
-# NOHINTS: invalid instruction encoding
 0x19 0x70
 
 # GOOD: c.lui zero, 1048551
-# NOHINTS: invalid instruction encoding
 0x1D 0x70
 
 # GOOD: c.lui zero, 1048552
-# NOHINTS: invalid instruction encoding
 0x21 0x70
 
 # GOOD: c.lui zero, 1048553
-# NOHINTS: invalid instruction encoding
 0x25 0x70
 
 # GOOD: c.lui zero, 1048554
-# NOHINTS: invalid instruction encoding
 0x29 0x70
 
 # GOOD: c.lui zero, 1048555
-# NOHINTS: invalid instruction encoding
 0x2D 0x70
 
 # GOOD: c.lui zero, 1048556
-# NOHINTS: invalid instruction encoding
 0x31 0x70
 
 # GOOD: c.lui zero, 1048557
-# NOHINTS: invalid instruction encoding
 0x35 0x70
 
 # GOOD: c.lui zero, 1048558
-# NOHINTS: invalid instruction encoding
 0x39 0x70
 
 # GOOD: c.lui zero, 1048559
-# NOHINTS: invalid instruction encoding
 0x3D 0x70
 
 # GOOD: c.lui zero, 1048560
-# NOHINTS: invalid instruction encoding
 0x41 0x70
 
 # GOOD: c.lui zero, 1048561
-# NOHINTS: invalid instruction encoding
 0x45 0x70
 
 # GOOD: c.lui zero, 1048562
-# NOHINTS: invalid instruction encoding
 0x49 0x70
 
 # GOOD: c.lui zero, 1048563
-# NOHINTS: invalid instruction encoding
 0x4D 0x70
 
 # GOOD: c.lui zero, 1048564
-# NOHINTS: invalid instruction encoding
 0x51 0x70
 
 # GOOD: c.lui zero, 1048565
-# NOHINTS: invalid instruction encoding
 0x55 0x70
 
 # GOOD: c.lui zero, 1048566
-# NOHINTS: invalid instruction encoding
 0x59 0x70
 
 # GOOD: c.lui zero, 1048567
-# NOHINTS: invalid instruction encoding
 0x5D 0x70
 
 # GOOD: c.lui zero, 1048568
-# NOHINTS: invalid instruction encoding
 0x61 0x70
 
 # GOOD: c.lui zero, 1048569
-# NOHINTS: invalid instruction encoding
 0x65 0x70
 
 # GOOD: c.lui zero, 1048570
-# NOHINTS: invalid instruction encoding
 0x69 0x70
 
 # GOOD: c.lui zero, 1048571
-# NOHINTS: invalid instruction encoding
 0x6D 0x70
 
 # GOOD: c.lui zero, 1048572
-# NOHINTS: invalid instruction encoding
 0x71 0x70
 
 # GOOD: c.lui zero, 1048573
-# NOHINTS: invalid instruction encoding
 0x75 0x70
 
 # GOOD: c.lui zero, 1048574
-# NOHINTS: invalid instruction encoding
 0x79 0x70
 
 # GOOD: c.lui zero, 1048575
-# NOHINTS: invalid instruction encoding
 0x7D 0x70
 
 # BAD: invalid instruction encoding
diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s
index 8dddbf887c87c..413573af1c5e6 100644
--- a/llvm/test/MC/RISCV/rv32c-invalid.s
+++ b/llvm/test/MC/RISCV/rv32c-invalid.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=+no-rvc-hints < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+c < %s 2>&1 \
 # RUN:     | FileCheck %s
-# RUN: not llvm-mc -triple=riscv32 -mattr=+zca -mattr=+no-rvc-hints < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zca < %s 2>&1 \
 # RUN:     | FileCheck %s
 
 ## GPRC
@@ -23,16 +23,10 @@ c.lwsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding
 c.lwsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
 c.jr  x0 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0)
 c.jalr  zero # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
-c.addi  x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero
-c.li  zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
-c.slli  zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
-c.mv  zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.mv  ra, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0)
 c.add  ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
-c.add  zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 ## GPRNoX0X2
-c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0) and sp (x2){{$}}
 
 ## SP
@@ -57,7 +51,6 @@ c.andi a0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer
 c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
 
 ## simm6nonzero
-c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
 c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
 c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]

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llvmbot commented Jun 21, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

As far as I know binutils does not have a similar option and I don't know of a reason we shouldn't accept the RVC hint instructions.

Full diff: https://github.com/llvm/llvm-project/pull/145138.diff

8 Files Affected:

  • (modified) llvm/docs/ReleaseNotes.md (+1)
  • (modified) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp (+1-1)
  • (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (-7)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+1-1)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+5-5)
  • (modified) llvm/test/CodeGen/RISCV/features-info.ll (-1)
  • (modified) llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt (-68)
  • (modified) llvm/test/MC/RISCV/rv32c-invalid.s (+2-9)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0395f43c61953..3713cc1e4161c 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -211,6 +211,7 @@ Changes to the RISC-V Backend
 * `-mcpu=sifive-x390` was added.
 * `-mtune=andes-45-series` was added.
 * Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
+* Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index d4d7de289a107..d12d033f878f9 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -292,7 +292,7 @@ void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
     NontemporalMode += 0b10;
 
   MCInst Hint;
-  if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
+  if (STI->hasStdExtCOrZca())
     Hint.setOpcode(RISCV::C_ADD_HINT);
   else
     Hint.setOpcode(RISCV::ADD);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6df6368929dac..224da07696fd0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -373,13 +373,6 @@ def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
 def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
 
 // Compressed Extensions
-def FeatureNoRVCHints
-    : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
-                       "Disable RVC Hint Instructions.">;
-def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
-                  AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
-                                     "RVC Hint Instructions">;
-
 def FeatureStdExtZca
     : RISCVExtension<1, 0,
                      "part of the C extension, excluding compressed "
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d9ef911b9a32e..bd6913362b516 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1717,7 +1717,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   if (!MI.memoperands_empty()) {
     MachineMemOperand *MMO = *(MI.memoperands_begin());
     if (STI.hasStdExtZihintntl() && MMO->isNonTemporal()) {
-      if (STI.hasStdExtCOrZca() && STI.enableRVCHintInstrs()) {
+      if (STI.hasStdExtCOrZca()) {
         if (isCompressibleInst(MI, STI))
           return 4; // c.ntl.all + c.load/c.store
         return 6;   // c.ntl.all + load/store
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index fd8591f5ab2d8..9c1db7ccef5ea 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -608,7 +608,7 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
 // HINT Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+let Predicates = [HasStdExtCOrZca], hasSideEffects = 0, mayLoad = 0,
     mayStore = 0 in {
 
 def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
@@ -691,24 +691,24 @@ def C_SRAI64_HINT : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
   let Inst{12} = 0;
 }
 
-} // Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+} // Predicates = [HasStdExtCOrZca], hasSideEffects = 0, mayLoad = 0,
   // mayStore = 0
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtCOrZca, HasRVCHints] in {
+let Predicates = [HasStdExtCOrZca] in {
 // Just a different syntax for the c.nop hint: c.addi x0, simm6 vs c.nop simm6.
 def : InstAlias<"c.addi x0, $imm", (C_NOP_HINT simm6nonzero:$imm), 0>;
 }
 
-let Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl] in {
+let Predicates = [HasStdExtC, HasStdExtZihintntl] in {
 def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
 def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
 def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
 def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
-} // Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl]
+} // Predicates = [HasStdExtC, HasStdExtZihintntl]
 
 let EmitPriority = 0 in {
 let Predicates = [HasStdExtCOrZca] in {
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 8b931f70aa5cc..999ecba7f1b9c 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -61,7 +61,6 @@
 ; CHECK-NEXT:   m                                - 'M' (Integer Multiplication and Division).
 ; CHECK-NEXT:   mips-p8700                       - MIPS p8700 processor.
 ; CHECK-NEXT:   no-default-unroll                - Disable default unroll preference..
-; CHECK-NEXT:   no-rvc-hints                     - Disable RVC Hint Instructions..
 ; CHECK-NEXT:   no-sink-splat-operands           - Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions.
 ; CHECK-NEXT:   no-trailing-seq-cst-fence        - Disable trailing fence for seq-cst store..
 ; CHECK-NEXT:   optimized-nf2-segment-load-store - vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle.
diff --git a/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt b/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt
index 17889c15cbf95..0a83a200c9317 100644
--- a/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt
+++ b/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt
@@ -10,265 +10,197 @@
 # RUN: llvm-mc --disassemble -triple=riscv32  -mattr=+c -mattr=+Zcmop \
 # RUN:     -M no-aliases --show-encoding < %s | \
 # RUN:   FileCheck --check-prefixes=GOOD,MOP %s
-#
-# RUN: llvm-mc --disassemble -triple=riscv32  -mattr=+c -mattr=+no-rvc-hints \
-# RUN:     -M no-aliases --show-encoding < %s 2>&1 | \
-# RUN:   FileCheck --check-prefix=NOHINTS %s
 
 # BAD: invalid instruction encoding
-# NOHINTS: invalid instruction encoding
 0x01 0x60
 
 # GOOD: c.lui zero, 1
-# NOHINTS: invalid instruction encoding
 0x05 0x60
 
 # GOOD: c.lui zero, 2
-# NOHINTS: invalid instruction encoding
 0x09 0x60
 
 # GOOD: c.lui zero, 3
-# NOHINTS: invalid instruction encoding
 0x0D 0x60
 
 # GOOD: c.lui zero, 4
-# NOHINTS: invalid instruction encoding
 0x11 0x060
 
 # GOOD: c.lui zero, 5
-# NOHINTS: invalid instruction encoding
 0x15 0x60
 
 # GOOD: c.lui zero, 6
-# NOHINTS: invalid instruction encoding
 0x19 0x60
 
 # GOOD: c.lui zero, 7
-# NOHINTS: invalid instruction encoding
 0x1D 0x60
 
 # GOOD: c.lui zero, 8
-# NOHINTS: invalid instruction encoding
 0x21 0x60
 
 # GOOD: c.lui zero, 9
-# NOHINTS: invalid instruction encoding
 0x25 0x60
 
 # GOOD: c.lui zero, 10
-# NOHINTS: invalid instruction encoding
 0x29 0x60
 
 # GOOD: c.lui zero, 11
-# NOHINTS: invalid instruction encoding
 0x2D 0x60
 
 # GOOD: c.lui zero, 12
-# NOHINTS: invalid instruction encoding
 0x31 0x60
 
 # GOOD: c.lui zero, 13
-# NOHINTS: invalid instruction encoding
 0x35 0x60
 
 # GOOD: c.lui zero, 14
-# NOHINTS: invalid instruction encoding
 0x39 0x60
 
 # GOOD: c.lui zero, 15
-# NOHINTS: invalid instruction encoding
 0x3D 0x60
 
 # GOOD: c.lui zero, 16
-# NOHINTS: invalid instruction encoding
 0x41 0x60
 
 # GOOD: c.lui zero, 17
-# NOHINTS: invalid instruction encoding
 0x45 0x60
 
 # GOOD: c.lui zero, 18
-# NOHINTS: invalid instruction encoding
 0x49 0x60
 
 # GOOD: c.lui zero, 19
-# NOHINTS: invalid instruction encoding
 0x4D 0x60
 
 # GOOD: c.lui zero, 20
-# NOHINTS: invalid instruction encoding
 0x51 0x60
 
 # GOOD: c.lui zero, 21
-# NOHINTS: invalid instruction encoding
 0x55 0x60
 
 # GOOD: c.lui zero, 22
-# NOHINTS: invalid instruction encoding
 0x59 0x60
 
 # GOOD: c.lui zero, 23
-# NOHINTS: invalid instruction encoding
 0x5D 0x60
 
 # GOOD: c.lui zero, 24
-# NOHINTS: invalid instruction encoding
 0x61 0x60
 
 # GOOD: c.lui zero, 25
-# NOHINTS: invalid instruction encoding
 0x65 0x60
 
 # GOOD: c.lui zero, 26
-# NOHINTS: invalid instruction encoding
 0x69 0x60
 
 # GOOD: c.lui zero, 27
-# NOHINTS: invalid instruction encoding
 0x6D 0x60
 
 # GOOD: c.lui zero, 28
-# NOHINTS: invalid instruction encoding
 0x71 0x60
 
 # GOOD: c.lui zero, 29
-# NOHINTS: invalid instruction encoding
 0x75 0x60
 
 # GOOD: c.lui zero, 30
-# NOHINTS: invalid instruction encoding
 0x79 0x60
 
 # GOOD: c.lui zero, 31
-# NOHINTS: invalid instruction encoding
 0x7D 0x60
 
 # GOOD: c.lui zero, 1048544
-# NOHINTS: invalid instruction encoding
 0x01 0x70
 
 # GOOD: c.lui zero, 1048545
-# NOHINTS: invalid instruction encoding
 0x05 0x70
 
 # GOOD: c.lui zero, 1048546
-# NOHINTS: invalid instruction encoding
 0x09 0x70
 
 # GOOD: c.lui zero, 1048547
-# NOHINTS: invalid instruction encoding
 0x0D 0x70
 
 # GOOD: c.lui zero, 1048548
-# NOHINTS: invalid instruction encoding
 0x11 0x70
 
 # GOOD: c.lui zero, 1048549
-# NOHINTS: invalid instruction encoding
 0x15 0x70
 
 # GOOD: c.lui zero, 1048550
-# NOHINTS: invalid instruction encoding
 0x19 0x70
 
 # GOOD: c.lui zero, 1048551
-# NOHINTS: invalid instruction encoding
 0x1D 0x70
 
 # GOOD: c.lui zero, 1048552
-# NOHINTS: invalid instruction encoding
 0x21 0x70
 
 # GOOD: c.lui zero, 1048553
-# NOHINTS: invalid instruction encoding
 0x25 0x70
 
 # GOOD: c.lui zero, 1048554
-# NOHINTS: invalid instruction encoding
 0x29 0x70
 
 # GOOD: c.lui zero, 1048555
-# NOHINTS: invalid instruction encoding
 0x2D 0x70
 
 # GOOD: c.lui zero, 1048556
-# NOHINTS: invalid instruction encoding
 0x31 0x70
 
 # GOOD: c.lui zero, 1048557
-# NOHINTS: invalid instruction encoding
 0x35 0x70
 
 # GOOD: c.lui zero, 1048558
-# NOHINTS: invalid instruction encoding
 0x39 0x70
 
 # GOOD: c.lui zero, 1048559
-# NOHINTS: invalid instruction encoding
 0x3D 0x70
 
 # GOOD: c.lui zero, 1048560
-# NOHINTS: invalid instruction encoding
 0x41 0x70
 
 # GOOD: c.lui zero, 1048561
-# NOHINTS: invalid instruction encoding
 0x45 0x70
 
 # GOOD: c.lui zero, 1048562
-# NOHINTS: invalid instruction encoding
 0x49 0x70
 
 # GOOD: c.lui zero, 1048563
-# NOHINTS: invalid instruction encoding
 0x4D 0x70
 
 # GOOD: c.lui zero, 1048564
-# NOHINTS: invalid instruction encoding
 0x51 0x70
 
 # GOOD: c.lui zero, 1048565
-# NOHINTS: invalid instruction encoding
 0x55 0x70
 
 # GOOD: c.lui zero, 1048566
-# NOHINTS: invalid instruction encoding
 0x59 0x70
 
 # GOOD: c.lui zero, 1048567
-# NOHINTS: invalid instruction encoding
 0x5D 0x70
 
 # GOOD: c.lui zero, 1048568
-# NOHINTS: invalid instruction encoding
 0x61 0x70
 
 # GOOD: c.lui zero, 1048569
-# NOHINTS: invalid instruction encoding
 0x65 0x70
 
 # GOOD: c.lui zero, 1048570
-# NOHINTS: invalid instruction encoding
 0x69 0x70
 
 # GOOD: c.lui zero, 1048571
-# NOHINTS: invalid instruction encoding
 0x6D 0x70
 
 # GOOD: c.lui zero, 1048572
-# NOHINTS: invalid instruction encoding
 0x71 0x70
 
 # GOOD: c.lui zero, 1048573
-# NOHINTS: invalid instruction encoding
 0x75 0x70
 
 # GOOD: c.lui zero, 1048574
-# NOHINTS: invalid instruction encoding
 0x79 0x70
 
 # GOOD: c.lui zero, 1048575
-# NOHINTS: invalid instruction encoding
 0x7D 0x70
 
 # BAD: invalid instruction encoding
diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s
index 8dddbf887c87c..413573af1c5e6 100644
--- a/llvm/test/MC/RISCV/rv32c-invalid.s
+++ b/llvm/test/MC/RISCV/rv32c-invalid.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=+no-rvc-hints < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+c < %s 2>&1 \
 # RUN:     | FileCheck %s
-# RUN: not llvm-mc -triple=riscv32 -mattr=+zca -mattr=+no-rvc-hints < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zca < %s 2>&1 \
 # RUN:     | FileCheck %s
 
 ## GPRC
@@ -23,16 +23,10 @@ c.lwsp  x0, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding
 c.lwsp  zero, 4(sp) # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
 c.jr  x0 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0)
 c.jalr  zero # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero (x0)
-c.addi  x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero
-c.li  zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
-c.slli  zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
-c.mv  zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.mv  ra, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0)
 c.add  ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
-c.add  zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 ## GPRNoX0X2
-c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0) and sp (x2){{$}}
 
 ## SP
@@ -57,7 +51,6 @@ c.andi a0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer
 c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
 
 ## simm6nonzero
-c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}}
 c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
 c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
 c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]

lenary
lenary approved these changes Jun 21, 2025
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I'm happy for this to land, but please wait for a little more consensus than that.

Looking at https://reviews.llvm.org/D62592 (where this landed), @asb said

We may later review whether the ability to enable/disable these hints is worth it or not (I know I'd been in favour from the start, but looking at it with fresh eyes I'm not sure it's fully necessary).

Apparently later means 6 years later.

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@lenary lenary lenary approved these changes

@asb asb Awaiting requested review from asb

@luismarques luismarques Awaiting requested review from luismarques

@preames preames Awaiting requested review from preames

@wangpc-pp wangpc-pp Awaiting requested review from wangpc-pp

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@topperc @llvmbot @lenary