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[AMDGPU] Support merging 16-bit TBUFFER load/store instruction #145078

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[AMDGPU] Support merging 16-bit TBUFFER load/store instruction #145078

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46 changes: 36 additions & 10 deletions llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1040,32 +1040,58 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
if (CI.Offset == Paired.Offset)
return false;

// Use 2-byte element size if both tbuffer formats are 16-bit.
unsigned EltSize = CI.EltSize;
auto Has16BitComponents = [&](unsigned Format) -> bool {
const auto *Info = AMDGPU::getGcnBufferFormatInfo(Format, STI);
return Info && Info->BitsPerComp == 16;
};

if ((CI.InstClass == TBUFFER_LOAD || CI.InstClass == TBUFFER_STORE)) {
// TODO: Support merging 8-bit tbuffer load/store instructions
if (Has16BitComponents(CI.Format) && Has16BitComponents(Paired.Format))
EltSize = 2;
}

// This won't be valid if the offset isn't aligned.
if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0))
if ((CI.Offset % EltSize != 0) || (Paired.Offset % EltSize != 0))
return false;

if (CI.InstClass == TBUFFER_LOAD || CI.InstClass == TBUFFER_STORE) {

const llvm::AMDGPU::GcnBufferFormatInfo *Info0 =
llvm::AMDGPU::getGcnBufferFormatInfo(CI.Format, STI);
const AMDGPU::GcnBufferFormatInfo *Info0 =
AMDGPU::getGcnBufferFormatInfo(CI.Format, STI);
if (!Info0)
return false;
const llvm::AMDGPU::GcnBufferFormatInfo *Info1 =
llvm::AMDGPU::getGcnBufferFormatInfo(Paired.Format, STI);
const AMDGPU::GcnBufferFormatInfo *Info1 =
AMDGPU::getGcnBufferFormatInfo(Paired.Format, STI);
if (!Info1)
return false;

if (Info0->BitsPerComp != Info1->BitsPerComp ||
Info0->NumFormat != Info1->NumFormat)
return false;

// TODO: Should be possible to support more formats, but if format loads
// are not dword-aligned, the merged load might not be valid.
if (Info0->BitsPerComp != 32)
// Buffer instructions support up to 4 components per access (e.g., x, xy,
// xyz, xyzw).
unsigned NumCombinedComponents = CI.Width + Paired.Width;
if (NumCombinedComponents > 4)
return false;

if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0)
if (getBufferFormatWithCompCount(CI.Format, NumCombinedComponents, STI) ==
0)
return false;

// Merge only when the two access ranges are strictly back-to-back,
// any gap or overlap can over-write data or leave holes.
unsigned BytePerComp = Info0->BitsPerComp / 8;
unsigned ElemIndex0 = CI.Offset / BytePerComp;
unsigned ElemIndex1 = Paired.Offset / BytePerComp;
if (!(ElemIndex0 + CI.Width == ElemIndex1 ||
ElemIndex1 + Paired.Width == ElemIndex0))
return false;

return true;
}

uint32_t EltOffset0 = CI.Offset / CI.EltSize;
Expand All @@ -1076,7 +1102,7 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
// Handle all non-DS instructions.
if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {
if (EltOffset0 + CI.Width != EltOffset1 &&
EltOffset1 + Paired.Width != EltOffset0)
EltOffset1 + Paired.Width != EltOffset0)
return false;
if (CI.CPol != Paired.CPol)
return false;
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