README: update.

README.md

@@ -1,15 +1,14 @@
 # Chryse
 
-A little framework to build projects in Chisel, but it might end up turning into
-its own HDL depending on how much I love Scala. :)
+A little framework to build HDL projects in Chisel with open-source toolchains.
 
 ## Examples
 
 * <https://github.com/kivikakk/sevsegsim>
 * <https://github.com/kivikakk/spifrbb> — used as part of a presentation on
-  CXXRTL at the Yosys Users Group ([slides])
+  CXXRTL at the Yosys Users Group ([transcript/slides][chisel-and-cxx])
 
-[slides]: https://f.hrzn.ee/chiselcxx.pdf
+[chisel-and-cxx]: https://kivikakk.ee/digital/2024/05/28/chisel-and-cxx/
 
 ```console
 $ sbt run
@@ -38,12 +37,14 @@ Run the C++ simulator tests.
 
 ## Quick feature overview
 
-* Provides an App that facilitates synthesis for multiple target platforms.
-* Boards provide resources — refer to them in your design, and Chryse adds them
-  to the PCF (or equivalent) used during build.
-* [CXXRTL] support: it's just another kind of platform. Chisel blackboxes are
-  automatically lowered into CXXRTL, and Chryse's build system takes care of the
-  details. You write the sim driver and blackbox implementations.
+* Provides an extensible App that facilitates synthesis for multiple target
+  platforms, and whatever other tasks you need.
+* Boards provide resources — refer to them in your design, and Chryse
+  instantiates the necessary IO buffers in-between and adds them to the
+  constraints used during place-and-route.
+* [CXXRTL] support: it's just another kind of platform. Chisel modules are
+  translated into CXXRTL blackboxes, you write the sim driver and blackbox
+  implementations, and the build system takes care of the details.
 
 [CXXRTL]: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/write_cxxrtl.html
 
@@ -52,12 +53,18 @@ Run the C++ simulator tests.
 ### Basic functionality/resources
 
 * iCE40: [iCEBreaker]
+  * Depends on [Project IceStorm] and [nextpnr].
 * ECP5: [ULX3S]
+  * Depends on [Project Trellis], [nextpnr] and [openFPGALoader].
 
 ### Planned
 
 * ECP5: [OrangeCrab]
 
 [iCEBreaker]: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/write_cxxrtl.html
+[Project IceStorm]: https://github.com/YosysHQ/icestorm
+[nextpnr]: https://github.com/YosysHQ/nextpnr
 [ULX3S]: https://radiona.org/ulx3s/
+[Project Trellis]: https://github.com/YosysHQ/prjtrellis
+[openFPGALoader]: https://github.com/trabucayre/openFPGALoader
 [OrangeCrab]: https://1bitsquared.com/products/orangecrab

src/main/scala/ee/hrzn/chryse/platform/ecp5/ULX3SPlatform.scala

@@ -49,8 +49,11 @@ class ULX3SPlatformResources extends PlatformBoardResources {
   // TODO: also expose RTS, DTR.
   var uart = UART()
     .onPins(rx = "M1", tx = "L4")
+  // TODO: either just unconditionally set this on, or only when uart.tx is
+  // accessed.
   var uartTxEnable = ResourceData(Output(Bool())).onPin("L3")
 
+  // TODO
   val led0 = LED().inverted.onPin("B2").withAttributes("DRIVE" -> 4)
   val led1 = LED().inverted.onPin("C2").withAttributes("DRIVE" -> 4)
   val led2 = LED().inverted.onPin("C1").withAttributes("DRIVE" -> 4)
@@ -72,6 +75,7 @@ class ULX3SPlatformResources extends PlatformBoardResources {
     )
     .withAttributes("PULLMODE" -> "NONE", "DRIVE" -> "4")
 
+  // TODO
   val butt0 = Button().inverted.onPin("D6").withAttributes("PULLMODE" -> "UP")
 // val buttons =
   // DIP switches