feat: implement x2apic support #86
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Some recent CPUs with LEGACY_XAPIC_DISABLED only support x2apic mode with SGX. In x2apic mode all APIC configuration needs to go through ring-0 RD/WRMSR instructions, which is also the only access mode supported for IA32_TSC_DEADLINE. cf issue #72
All selftests should now be compatible with both legacy xapic MMIO and x2apic MSR addressing modes via libsgxstep support for privileged rdmsr/wrmsr call gates. cf issue #72
This further increases the latency of the ucode-assisted page-table walk for the first instruction following ERESUME and thus the landing space for SGX-Step's timer interrupt.
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Some recent CPUs with LEGACY_XAPIC_DISABLED only support x2apic mode with SGX.
In x2apic mode all APIC configuration needs to go through ring-0 RD/WRMSR
instructions, which is also the only access mode supported for
IA32_TSC_DEADLINE.
Fixes #72