Migrate crate to use new derive macro, clean old cobweb code

derive/src/chips.rs

@@ -3,58 +3,40 @@
 #[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
 pub struct Chip {
     pub name: &'static str,
-    pub address_size: u16,
     pub register_size: u16,
-    pub parity: bool,
 }
 
 pub const CHIPS: [Chip; 8] = [
     Chip {
         name: "a4910",
-        address_size: 2,
         register_size: 13,
-        parity: false,
     },
     Chip {
         name: "a4962",
-        address_size: 3,
         register_size: 12,
-        parity: false,
     },
     Chip {
         name: "a4963",
-        address_size: 3,
         register_size: 12,
-        parity: false,
     },
     Chip {
         name: "a4964",
-        address_size: 5,
         register_size: 9,
-        parity: true,
     },
     Chip {
         name: "amt49100",
-        address_size: 5,
         register_size: 9,
-        parity: true,
     },
     Chip {
         name: "amt49100",
-        address_size: 5,
         register_size: 9,
-        parity: true,
     },
     Chip {
         name: "amt49100",
-        address_size: 5,
         register_size: 9,
-        parity: true,
     },
     Chip {
         name: "amt49100",
-        address_size: 5,
         register_size: 9,
-        parity: true,
     },
 ];

derive/src/lib.rs

@@ -10,106 +10,30 @@ use syn::{parse_macro_input, DeriveInput};
 
 mod chips;
 
-// #[proc_macro_derive(AllegroRegister)]
-// pub fn allegro_derive(item: TokenStream) -> TokenStream {
-//     let DeriveInput {ident, attrs, ..} = parse_macro_input!(item as DeriveInput);
-
-//     let bitsize = analyze_bitsize(&attrs);
-
-//     quote! {
-//         impl crate::regs::AllegroRegister<bilge::prelude::UInt<usize, #bitsize>> for #ident {
-//             fn get_value(&self) -> u16 {
-//                 self.value.into()
-//             }
-
-//             fn set_value(&mut self, value: bilge::prelude::UInt<usize, #bitsize>) {
-//                 self.value = value;
-//             }
-//         }
-//     }.into()
-// }
-
-// fn analyze_bitsize(attrs: &Vec<syn::Attribute>) -> u16 {
-//     let mut bitsizes = attrs.iter().filter_map(|attr| {
-//         if attr.path().is_ident("bitsize") {
-//             let a: syn::LitInt = attr.parse_args().unwrap();
-//             Some(a.base10_parse::<u16>().unwrap())
-//         } else {
-//             None
-//         }
-//     });
-
-//     match bitsizes.next() {
-//         Some(bitsize) => bitsize,
-//         None => panic!("'bitsize' not found in object attributes."),
-//     }
-// }
-
-
 /// Derive macro to implement the allegro_motor_drivers::regs::AllegroRegister trait.
 ///
-/// Please note that a compile failure will occur if derive macros are defined in the wrong order,
-/// or if the bitsize derive macro is not used at all. This occurs because derive macros are parsed
-/// from the outside in, and each macro depends on implementations defined by other macros.
-/// ```compile_fail
-/// #[allegro_register(chip = "a4910")]
-/// struct MyStruct {
-///     field_1: bool,
-/// }
-/// ```
-///
-/// ```compile_fail
-/// #[bitsize(1)]
-/// #[allegro_register(chip = "a4910")]
-/// struct MyStruct {
-///     field_1: bool,
-/// }
-/// ```
-///
 #[proc_macro_derive(AllegroRegister)]
 pub fn allegro_derive(item: TokenStream) -> TokenStream {
     let DeriveInput { ident, .. } = parse_macro_input!(item as DeriveInput);
 
     let source_file = proc_macro::Span::call_site().source_file().clone().path();
     let chip_name = source_file.iter().nth(2).unwrap().to_str().unwrap();
-    let chip = chips::CHIPS.into_iter().find(|chip| {chip.name == chip_name}).unwrap();
+    let chip = chips::CHIPS
+        .into_iter()
+        .find(|chip| chip.name == chip_name)
+        .unwrap();
     let bitsize = proc_macro2::Literal::u16_unsuffixed(chip.register_size);
 
     quote! {
         impl crate::regs::AllegroRegister<bilge::prelude::UInt<u16, #bitsize>> for #ident {
             fn get_value(&self) -> u16 {
                 self.value.into()
             }
-        
+
             fn set_value(&mut self, value: bilge::prelude::UInt<u16, #bitsize>) {
                 self.value = value;
             }
         }
     }
     .into()
 }
-
-// fn analyze_chip(attrs: &[syn::Attribute]) -> Result<chips::Chip, syn::Error> {
-//     let mut selected_chip = chips::Chip::default();
-
-//     for attr in attrs.iter() {
-//         if attr.path().is_ident("allegro_register") {
-//             attr.parse_nested_meta(|meta| {
-//                 if meta.path.is_ident("chip") {
-//                     let value = meta.value()?;
-//                     let str: syn::LitStr = value.parse()?;
-//                     let valid_chip = chips::CHIPS
-//                         .into_iter()
-//                         .find(|chip| {*chip.name == str.value()})
-//                         .ok_or_else(|| meta.error("Invalid chip name"))?;
-//                     selected_chip = valid_chip;
-//                     Ok(())
-//                 } else {
-//                     let error_msg = r#"Register must provide a chip identifier, e.g. '#[allegro_register(chip = "a4910"))]'"#;
-//                     Err(meta.error(error_msg))
-//                 }
-//             })?;
-//         }
-//     }
-//     Ok(selected_chip)
-// }

drivers/src/a4910/driver.rs

@@ -42,18 +42,15 @@ where
     }
 }
 
-
 mod tests {
     #[test]
     fn test_spi_derive() {
         use super::*;
         use embedded_hal_mock::spi::{Mock, Transaction};
 
-        let expected_transfers = [
-            Transaction::transfer(vec![1, 2], vec![3, 4])
-        ];
+        let expected_transfers = [Transaction::transfer(vec![1, 2], vec![3, 4])];
         let spi_device = Mock::new(&expected_transfers);
-        
+
         let a4910 = A4910::new(spi_device);
 
         assert_eq!(a4910.read_request(A4910Reg::Config0), 0b00_0_0000000000000);
@@ -66,5 +63,4 @@ mod tests {
         // c1.read_response(0b00_0_0_0_11_1_1_1011111);
         // assert_eq!(c1.vt(), u7::new(0b1011111).into());
     }
-
 }

drivers/src/a4910/regs/config.rs

@@ -5,8 +5,8 @@ extern crate allegro_motor_derive;
 use allegro_motor_derive::AllegroRegister;
 use bilge::prelude::*;
 
-use crate::regs::ConstantAddress;
 use super::A4910Reg;
+use crate::regs::ConstantAddress;
 
 #[bitsize(6)]
 #[derive(Clone, Copy, DebugBits, PartialEq, FromBits)]

drivers/src/a4910/regs/mask.rs

@@ -5,8 +5,8 @@
 use allegro_motor_derive::AllegroRegister;
 use bilge::prelude::*;
 
-use crate::regs::ConstantAddress;
 use super::A4910Reg;
+use crate::regs::ConstantAddress;
 
 #[bitsize(13)]
 #[derive(PartialEq, Clone, Copy, DebugBits, Default, FromBits, AllegroRegister)]
@@ -28,4 +28,4 @@ pub struct Mask {
 
 impl ConstantAddress<A4910Reg> for Mask {
     const ADDRESS: A4910Reg = A4910Reg::Mask;
-}
+}

drivers/src/a4910/regs/run.rs

@@ -1,10 +1,10 @@
 //! Run configuration register
 
-use bilge::prelude::*;
 use allegro_motor_derive::AllegroRegister;
+use bilge::prelude::*;
 
-use crate::regs::ConstantAddress;
 use super::A4910Reg;
+use crate::regs::ConstantAddress;
 
 #[bitsize(13)]
 #[derive(PartialEq, Clone, Copy, DebugBits, Default, FromBits, AllegroRegister)]
@@ -18,16 +18,6 @@ pub struct Run {
     reserved: u7,
 }
 
-// impl AllegroRegister<u13> for Run {
-//     fn get_value(&self) -> u16 {
-//         self.value.into()
-//     }
-
-//     fn set_value(&mut self, value: u13) {
-//         self.value = value;
-//     }
-// }
-
 impl ConstantAddress<A4910Reg> for Run {
     const ADDRESS: A4910Reg = A4910Reg::Run;
 }

drivers/src/lib.rs

@@ -13,4 +13,4 @@ pub mod amt49106;
 pub mod amt49107;
 
 pub mod io;
-pub mod regs;
+pub mod regs;