Generating Hardware IP (Verilog)

There are several examples in Halide-HLS/apps/hls_examples. The supported example applications are listed in Halide-HLS/apps/hls_examples/app.txt. They have similar file structure and can be built with the make command.

1. generating hardware accelerator design.

    cd Halide-HLS/apps/hls_examples/[app_name]
    make pipeline_hls.cpp
   

   The command generates a HLS kernel (hls_target.cpp) and a C test wrapper (pipeline_hls.cpp) for the application. The accelerator kernel design hls_target.cpp can be synthesized to Verilog using Vivado HLS compiler.

2. Running C simulation. The simulation verifies the functionality of HLS C design by checking the outputs with the Halide CPU implementation reference.

    make out.png
   

3. Synthesizing HLS C with Vivado HLS (version 2015.4 required). vivado_hls command needs to be found in PATH.

    make run_hls
   

   The default script Halide-HLS/apps/hls_examples/hls_support/run_hls.tcl runs through C simulation, C synthesis, post-synthesis simulation (usually slow), and IP packaging. Comment out corresponding commands in the script to skip any stages.

4. Analyzing HLS results using Vivado HLS GUI. Refer to the HLS tool document for more usage.

    vivado_hls -p hls_prj