Releases: jdryg/RISCVEmu
Releases · jdryg/RISCVEmu
Multi-cycle CPU w/ Caches
Multi-cycle CPU with separate L1 Instruction and Data caches on a shared bus.
Instructions
- Unzip the hdd_32MB_test_progs.zip from the bin folder.
- Run the emulator
- Select the bios executable from the bios/src directory
- Select the vhd from the bin directory (where you extracted the zip in step 1).
- Select the CPU type you would like to emulate
- Press Start and then the play button at the top of the debugger.
First binary release
Single-cycle CPU implementation with (potentially) multiple memory reads and writes per cycle.
Instructions
- Unzip the hdd_32MB_test_progs.zip from the bin folder.
- Run the emulator
- Select the bios executable from the bios/src directory
- Select the vhd from the bin directory (where you extracted the zip in step 1).
- Press Start and then the play button at the top of the debugger.