mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board.

The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
jaenrig-ifx · Nov 17, 2022 · 5e990cc · 5e990cc
1 parent d1ed0f1
commit 5e990cc
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Showing 53 changed files with 3,012 additions and 351 deletions.
diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile
@@ -101,13 +101,12 @@ SRC_ETH_C += \
 	hal/phy/device/phydp83848/fsl_phydp83848.c \
 	hal/phy/device/phyksz8081/fsl_phyksz8081.c \
 	hal/phy/device/phylan8720/fsl_phylan8720.c \
+	hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c \
 	hal/phy/mdio/enet/fsl_enet_mdio.c
 endif
 
 # NXP SDK sources
 SRC_HAL_IMX_C += \
-	$(MCU_DIR)/drivers/fsl_adc.c \
-	$(MCU_DIR)/drivers/fsl_cache.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_common.c \
 	$(MCU_DIR)/drivers/fsl_dmamux.c \
@@ -124,10 +123,9 @@ SRC_HAL_IMX_C += \
 	$(MCU_DIR)/drivers/fsl_pwm.c \
 	$(MCU_DIR)/drivers/fsl_sai.c \
 	$(MCU_DIR)/drivers/fsl_snvs_lp.c \
-	$(MCU_DIR)/drivers/fsl_trng.c \
 	$(MCU_DIR)/drivers/fsl_wdog.c \
-	$(MCU_DIR)/system_$(MCU_SERIES).c \
-	hal/fsl_flexspi_nor_boot.c \
+	$(MCU_DIR)/system_$(MCU_SERIES)$(MCU_CORE).c \
+	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
 
 ifeq ($(MICROPY_HW_SDRAM_AVAIL),1)
 SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_semc.c
@@ -137,11 +135,29 @@ ifeq ($(MICROPY_PY_MACHINE_SDCARD),1)
 SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_usdhc.c
 endif
 
-ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064))
+ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
 SRC_HAL_IMX_C += \
 	$(MCU_DIR)/drivers/fsl_qtmr.c
 endif
 
+ifeq ($(MCU_SERIES), MIMXRT1176)
+INC += -I$(TOP)/$(MCU_DIR)/drivers/cm7
+
+SRC_HAL_IMX_C += \
+	$(MCU_DIR)/drivers/cm7/fsl_cache.c \
+	$(MCU_DIR)/drivers/fsl_dcdc.c \
+	$(MCU_DIR)/drivers/fsl_pmu.c \
+	$(MCU_DIR)/drivers/fsl_common_arm.c \
+	$(MCU_DIR)/drivers/fsl_anatop_ai.c \
+	$(MCU_DIR)/drivers/fsl_caam.c \
+	$(MCU_DIR)/drivers/fsl_lpadc.c
+else
+SRC_HAL_IMX_C += \
+	$(MCU_DIR)/drivers/fsl_adc.c \
+	$(MCU_DIR)/drivers/fsl_cache.c \
+	$(MCU_DIR)/drivers/fsl_trng.c
+endif
+
 # C source files
 SRC_C += \
 	board_init.c \
@@ -243,7 +259,7 @@ SUPPORTS_HARDWARE_FP_DOUBLE = 0
 
 # Assembly source files
 SRC_SS = \
-	$(MCU_DIR)/gcc/startup_$(MCU_SERIES).S \
+	$(MCU_DIR)/gcc/startup_$(MCU_SERIES)$(MCU_CORE).S \
 	hal/resethandler_MIMXRT10xx.S
 
 SRC_S += shared/runtime/gchelper_m3.s \
@@ -279,11 +295,11 @@ CFLAGS += \
 	-D__STARTUP_INITIALIZE_RAMFUNCTION \
 	-DBOARD_$(BOARD) \
 	-DBOARD_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
-	-DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX \
+	-DCFG_TUSB_MCU=OPT_MCU_MIMXRT \
 	-DCLOCK_CONFIG_H='<boards/$(MCU_SERIES)_clock_config.h>' \
-	-DCPU_$(MCU_SERIES) \
+	-DCPU_$(MCU_SERIES)$(MCU_CORE) \
 	-DCPU_$(MCU_VARIANT) \
-	-DCPU_HEADER_H='<$(MCU_SERIES).h>' \
+	-DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \
 	-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
 	-DI2C_RETRY_TIMES=1000000 \
 	-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
@@ -438,9 +454,8 @@ $(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h
 
 $(GEN_FLEXRAM_CONFIG_SRC):
 	$(ECHO) "Create $@"
-	$(Q)$(PYTHON) $(MAKE_FLEXRAM_LD) -d $(TOP)/$(MCU_DIR)/$(MCU_SERIES).h \
-		-f $(TOP)/$(MCU_DIR)/$(MCU_SERIES)_features.h -l boards/$(MCU_SERIES).ld -c $(MCU_SERIES) > $(GEN_FLEXRAM_CONFIG_SRC)
-
+	$(Q)$(PYTHON) $(MAKE_FLEXRAM_LD) -d $(TOP)/$(MCU_DIR)/$(MCU_SERIES)$(MCU_CORE).h \
+		-f $(TOP)/$(MCU_DIR)/$(MCU_SERIES)$(MCU_CORE)_features.h -l boards/$(MCU_SERIES).ld -c $(MCU_SERIES) > $(GEN_FLEXRAM_CONFIG_SRC)
 
 # Use a pattern rule here so that make will only call make-pins.py once to make
 # both pins_gen.c and pins.h

diff --git a/ports/mimxrt/board_init.c b/ports/mimxrt/board_init.c
@@ -40,51 +40,32 @@
 #include CLOCK_CONFIG_H
 #include "modmachine.h"
 
-
 const uint8_t dcd_data[] = { 0x00 };
 
+void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn);
+
 void board_init(void) {
+    // Clean and enable cache
+    SCB_CleanDCache();
+    SCB_EnableDCache();
+    SCB_EnableICache();
     // Init clock
     BOARD_BootClockRUN();
     SystemCoreClockUpdate();
 
     // Enable IOCON clock
     CLOCK_EnableClock(kCLOCK_Iomuxc);
 
-    // ------------- SDRAM ------------ //
+    // SDRAM
     #if MICROPY_HW_SDRAM_AVAIL
     mimxrt_sdram_init();
     #endif
 
     // 1ms tick timer
     SysTick_Config(SystemCoreClock / 1000);
 
-    // ------------- USB0 ------------- //
-    // Clock
-    CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-    CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
-
-    #ifdef USBPHY1
-    USBPHY_Type *usb_phy = USBPHY1;
-    #else
-    USBPHY_Type *usb_phy = USBPHY;
-    #endif
-
-    // Enable PHY support for Low speed device + LS via FS Hub
-    usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-    // Enable all power for normal operation
-    usb_phy->PWD = 0;
-
-    // TX Timing
-    uint32_t phytx = usb_phy->TX;
-    phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-    phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-    usb_phy->TX = phytx;
-
-    // USB1
-    //  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-    //  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
+    // USB0
+    usb_phy0_init(0b0111, 0b0110, 0b0110);  // Configure nominal values for D_CAL and TXCAL45DP/DN
 
     // ADC
     machine_adc_init();
@@ -99,6 +80,49 @@ void board_init(void) {
     #endif
     // RTC
     machine_rtc_start();
+
+    // OCRAM wait states (discarded, but code kept)
+    #if 0
+    MECC1->PIPE_ECC_EN =
+        MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) |
+        MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) |
+        MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) |
+        MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1);
+
+    MECC2->PIPE_ECC_EN =
+        MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) |
+        MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) |
+        MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) |
+        MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1);
+
+    FLEXRAM->FLEXRAM_CTRL =
+        FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(1) |
+        FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(1) |
+        FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(1) |
+        FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(1);
+    #endif
+}
+
+void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn) {
+    #ifdef USBPHY1
+    USBPHY_Type *usb_phy = USBPHY1;
+    #else
+    USBPHY_Type *usb_phy = USBPHY;
+    #endif
+
+    CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
+    CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
+
+    #if defined(MIMXRT117x_SERIES)
+    usb_phy->TRIM_OVERRIDE_EN = USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(1) |
+        USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(1) |
+        USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(1) |
+        USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(1) |
+        USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(1);  // Enable override for D_CAL and TXCAL45DP/DN
+    #endif
+    usb_phy->PWD = 0U;  // Set all bits in PWD register to normal operation
+    usb_phy->TX = ((usb_phy->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
+        (USBPHY_TX_D_CAL(d_cal) | USBPHY_TX_TXCAL45DP(txcal45dp) | USBPHY_TX_TXCAL45DM(txcal45dn)));  // Configure values for D_CAL and TXCAL45DP/DN
 }
 
 void USB_OTG1_IRQHandler(void) {

diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h
@@ -54,6 +54,7 @@
 #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx }
 #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx }
 #define I2S_WM8960_RX_MODE  (1)
+#define I2S_AUDIO_PLL_CLOCK (2U)
 
 #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
     { \

diff --git a/ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h
@@ -59,6 +59,7 @@
 #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
 #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
 #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
+#define I2S_AUDIO_PLL_CLOCK (2U)
 
 #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
     { \

diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h
@@ -73,6 +73,7 @@
 #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
 #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
 #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
+#define I2S_AUDIO_PLL_CLOCK (2U)
 
 #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
     { \
@@ -158,8 +159,8 @@
 #define ENET_PHY_OPS        phyksz8081_ops
 
 // Etherner PIN definitions
-#define ENET_RESET_PIN      pin_GPIO_AD_B0_04
-#define ENET_INT_PIN        pin_GPIO_AD_B1_06
+#define ENET_RESET_PIN      &pin_GPIO_AD_B0_04
+#define ENET_INT_PIN        &pin_GPIO_AD_B1_06
 
 #define IOMUX_TABLE_ENET \
     { IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1, 0xB0E9u }, \

diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
@@ -62,6 +62,7 @@
 #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
 #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
 #define I2S_WM8960_RX_MODE  (1)
+#define I2S_AUDIO_PLL_CLOCK (2U)
 
 #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
     { \
@@ -148,8 +149,8 @@
 #define ENET_PHY_OPS        phyksz8081_ops
 
 // Etherner PIN definitions
-#define ENET_RESET_PIN      pin_GPIO_AD_B0_09
-#define ENET_INT_PIN        pin_GPIO_AD_B0_10
+#define ENET_RESET_PIN      &pin_GPIO_AD_B0_09
+#define ENET_INT_PIN        &pin_GPIO_AD_B0_10
 
 #define IOMUX_TABLE_ENET \
     { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \

diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h
@@ -62,6 +62,7 @@
 #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
 #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
 #define I2S_WM8960_RX_MODE  (1)
+#define I2S_AUDIO_PLL_CLOCK (2U)
 
 #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
     { \
@@ -146,8 +147,8 @@
 #define ENET_PHY_OPS        phyksz8081_ops
 
 // Etherner PIN definitions
-#define ENET_RESET_PIN      pin_GPIO_AD_B0_09
-#define ENET_INT_PIN        pin_GPIO_AD_B0_10
+#define ENET_RESET_PIN      &pin_GPIO_AD_B0_09
+#define ENET_INT_PIN        &pin_GPIO_AD_B0_10
 
 #define IOMUX_TABLE_ENET \
     { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \

diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h
@@ -62,6 +62,7 @@
 #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
 #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
 #define I2S_WM8960_RX_MODE  (1)
+#define I2S_AUDIO_PLL_CLOCK (2U)
 
 #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
     { \
@@ -146,8 +147,8 @@
 #define ENET_PHY_OPS        phyksz8081_ops
 
 // Etherner PIN definitions
-#define ENET_RESET_PIN      pin_GPIO_AD_B0_09
-#define ENET_INT_PIN        pin_GPIO_AD_B0_10
+#define ENET_RESET_PIN      &pin_GPIO_AD_B0_09
+#define ENET_INT_PIN        &pin_GPIO_AD_B0_10
 
 #define IOMUX_TABLE_ENET \
     { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \

diff --git a/ports/mimxrt/boards/MIMXRT1170_EVK/board.json b/ports/mimxrt/boards/MIMXRT1170_EVK/board.json
@@ -0,0 +1,28 @@
+{
+    "deploy": [
+        "../deploy_mimxrt.md"
+    ],
+    "docs": "",
+    "features": [
+        "Ethernet",
+        "SDRAM",
+        "MicroSD",
+        "MicroUSB",
+        "Microphone",
+        "AudioCodec",
+        "SPDIF",
+        "CAN",
+        "Camera",
+        "SIM Socket",
+        "OpenSDA",
+        "JLink"
+    ],
+    "images": [
+        "IMX-RT1170-EVK-TOP.jpg"
+    ],
+    "mcu": "mimxrt",
+    "product": "MIMXRT1170_EVK",
+    "thumbnail": "",
+    "url": "https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK",
+    "vendor": "NXP"
+}