Add support for the nRF5340

CMakeLists.txt

@@ -34,7 +34,7 @@ endif()
 
 # Define ARM_TARGET property
 set(ARM_TARGET STM32F407 CACHE STRING "Target for which the samples are build")
-set(ARM_TARGET_VALUES "NRF52840;STM32F407;STM32F411XE;STM32F446;STM32F4XX;STM32F746;STM32L4R5;STM32L476;CORSTONE-300" CACHE INTERNAL "List of possible targets")
+set(ARM_TARGET_VALUES "NRF52840;NRF5340;STM32F407;STM32F411XE;STM32F446;STM32F4XX;STM32F746;STM32L4R5;STM32L476;CORSTONE-300" CACHE INTERNAL "List of possible targets")
 set_property(CACHE ARM_TARGET PROPERTY STRINGS ${ARM_TARGET_VALUES})
 string(TOUPPER "${ARM_TARGET}" ARM_TARGET)
 
@@ -61,9 +61,9 @@ endif()
 if(ARM_TARGET STREQUAL "STM32L4R5" AND USE_UART1)
   message(FATAL_ERROR "UART1 is not supported for STM32L4R5")
 endif()
-# We don't support UART1 and UART2 on NRF52840
-if(ARM_TARGET STREQUAL "NRF52840" AND (USE_UART1 OR USE_UART2))
-  message(FATAL_ERROR "UART1 and UART2 are not supported for NF528400")
+# We don't support UART1 and UART2 on any NRF board
+if(ARM_TARGET MATCHES "^NRF" AND (USE_UART1 OR USE_UART2))
+  message(FATAL_ERROR "UART1 and UART2 are not supported for NRF boards")
 endif()
 
 # Define CLOCK_SOURCE property

README.md

@@ -14,7 +14,9 @@ This projects demonstrates how to build [IREE](https://github.com/openxla/iree)
 
 ## Target Support
 
-The samples can be build for several [STM32 32-bit Arm Cortex MCUs](https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html), for the [Nordic nRF52840 SoC](https://www.nordicsemi.com/products/nrf52840)
+The samples can be build for several [STM32 32-bit Arm Cortex MCUs](https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html),
+for the [Nordic nRF52840 SoC](https://www.nordicsemi.com/products/nrf52840),
+for the application core of the [Nordic nRF5340 SoC](https://www.nordicsemi.com/products/nrf5340)
 and for the Arm [Corstone-300](https://developer.arm.com/Processors/Corstone-300).
 
 ## Getting Started

build_tools/configure_build.sh

@@ -59,6 +59,14 @@ case $2 in
     fi
     ;;
 
+  nrf5340)
+    echo "Building for NRF5340"
+    export ARM_CPU="cortex-m33"
+    if [ -z ${PATH_TO_LINKER_SCRIPT+x} ]; then
+      export PATH_TO_LINKER_SCRIPT="${PATH_TO_REPO}/third_party/nrfx-custom/nrf5340_xxaa_application.ld"
+    fi
+    ;;
+
   stm32f407)
     echo "Building for STM32F407"
     export ARM_CPU="cortex-m4"
@@ -128,6 +136,7 @@ case $2 in
   *)
     echo "Unknown device. Supported devices are"
     echo "  'nrf52840'"
+    echo "  'nrf5340'"
     echo "  'stm32f407'"
     echo "  'stm32f411xe'"
     echo "  'stm32f446'"
@@ -146,6 +155,10 @@ case $2 in
     UART=0
     ;;
 
+  nrf5340)
+    UART=0
+    ;;
+
   *)
     UART=2
     ;;

build_tools/third_party/nrfx/CMakeLists.txt

@@ -35,6 +35,35 @@ target_compile_definitions(nrfx_nrf52840
 # Allow ld to find generic linker script
 target_link_directories(nrfx_nrf52840 INTERFACE "${nrfx_custom_DIR}")
 
+#-------------------------------------------------------------------------------
+# nRF5340
+#-------------------------------------------------------------------------------
+
+add_library(nrfx_nrf5340 STATIC "")
+
+target_sources(nrfx_nrf5340
+  PRIVATE
+    ${nrfx_DIR}/mdk/system_nrf5340_application.c
+    ${nrfx_custom_DIR}/gcc_startup_nrf5340_application.S
+)
+
+target_include_directories(nrfx_nrf5340
+  PUBLIC
+    ${CMSIS_5_SOURCE_DIR}/CMSIS/Core/Include/
+  PRIVATE
+    ${nrfx_DIR}/mdk/
+)
+
+target_compile_definitions(nrfx_nrf5340
+  PUBLIC
+    NRF5340_XXAA
+    NRF5340_XXAA_APPLICATION
+    NRF_APPLICATION
+)
+
+# Allow ld to find generic linker script
+target_link_directories(nrfx_nrf5340 INTERFACE "${nrfx_custom_DIR}")
+
 #-------------------------------------------------------------------------------
 # nRF UART
 #-------------------------------------------------------------------------------
@@ -69,3 +98,41 @@ if(ARM_TARGET STREQUAL "NRF52840")
       nrfx_nrf52840
   )
 endif()
+
+#-------------------------------------------------------------------------------
+# nRF UARTE
+#-------------------------------------------------------------------------------
+
+add_library(nrfx_uarte STATIC "")
+
+target_sources(nrfx_uarte
+  PRIVATE
+    ${nrfx_DIR}/drivers/src/nrfx_uarte.c
+    ${nrfx_DIR}/soc/nrfx_atomic.c
+)
+
+target_include_directories(nrfx_uarte
+  PUBLIC
+    ${nrfx_custom_DIR}
+    ${nrfx_DIR}
+    ${nrfx_DIR}/drivers/include/
+    ${nrfx_DIR}/hal/
+    ${nrfx_DIR}/templates/
+    ${nrfx_DIR}/mdk/
+    ${nrfx_DIR}/soc/
+)
+
+if(USE_UART0)
+  target_compile_definitions(nrfx_uarte
+    PUBLIC
+      NRFX_UARTE_ENABLED
+      NRFX_UARTE0_ENABLED
+  )
+endif()
+
+if(ARM_TARGET STREQUAL "NRF5340")
+  target_link_libraries(nrfx_uarte
+  PRIVATE
+    nrfx_nrf5340
+)
+endif()

samples/CMakeLists.txt

@@ -7,6 +7,8 @@
 if(BUILD_WITH_CMSIS)
   if(ARM_TARGET STREQUAL "NRF52840")
     set(CONDITIONAL_DEP nrfx_nrf52840)
+  elseif(ARM_TARGET STREQUAL "NRF5340")
+    set(CONDITIONAL_DEP nrfx_nrf5340)
   elseif(ARM_TARGET STREQUAL "STM32F407" OR ARM_TARGET STREQUAL "STM32F4XX")
     set(CONDITIONAL_DEP cmsis_device_f407xx)
   elseif(ARM_TARGET STREQUAL "STM32F411XE")

third_party/nrfx-custom/nrfx.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
+ * Copyright 2023 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -37,6 +38,10 @@
 #include <nrfx_config.h>
 #include <drivers/nrfx_common.h>
 #include <nrfx_glue.h>
+#undef NRFX_ATOMIC_FETCH_OR
+#undef NRFX_ATOMIC_FETCH_AND
+#undef nrfx_atomic_t
+#include <nrfx_glue_nrf5340.h>
 #include <hal/nrf_common.h>
 #include <haly/nrfy_common.h>
 #include <drivers/nrfx_errors.h>

third_party/nrfx-custom/nrfx_glue_nrf5340.h

@@ -0,0 +1,27 @@
+// SPDX-FileCopyrightText: 2023 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
+// SPDX-License-Identifier: BSD-3-Clause
+
+#ifndef NRFX_GLUE_NRFX5340_H__
+#define NRFX_GLUE_NRFX5340_H__
+
+// File providing macros as requested in `nrfx_glue.h`.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <nrfx_atomic.h>
+
+#define nrfx_atomic_t nrfx_atomic_u32_t
+
+#define NRFX_ATOMIC_FETCH_OR(p_data, value) \
+  nrfx_atomic_u32_fetch_or(p_data, value)
+
+#define NRFX_ATOMIC_FETCH_AND(p_data, value) \
+  nrfx_atomic_u32_fetch_and(p_data, value)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // NRFX_GLUE_NRFX5340_H__

utils/CMakeLists.txt

@@ -8,6 +8,9 @@ if(BUILD_WITH_CMSIS)
   if(ARM_TARGET STREQUAL "NRF52840")
     set(UTILS_SRC ${CMAKE_CURRENT_SOURCE_DIR}/nrf52840_cmsis.c)
     set(WRITE_SRC ${CMAKE_CURRENT_SOURCE_DIR}/write.c)
+  elseif(ARM_TARGET STREQUAL "NRF5340")
+    set(UTILS_SRC ${CMAKE_CURRENT_SOURCE_DIR}/nrf5340_cmsis.c)
+    set(WRITE_SRC ${CMAKE_CURRENT_SOURCE_DIR}/write.c)
   elseif(ARM_TARGET MATCHES "^STM32F4")
     set(UTILS_SRC ${CMAKE_CURRENT_SOURCE_DIR}/stm32f4_cmsis.c)
   elseif(ARM_TARGET MATCHES "^STM32F7")
@@ -45,6 +48,10 @@ if(ARM_TARGET STREQUAL "NRF52840")
   target_link_libraries(utils PRIVATE nrfx_uart)
 endif()
 
+if(ARM_TARGET STREQUAL "NRF5340")
+  target_link_libraries(utils PRIVATE nrfx_uarte)
+endif()
+
 if(USE_UART0)
   target_compile_definitions(utils PRIVATE USE_UART0)
 endif()

utils/nrf5340_cmsis.c

@@ -0,0 +1,44 @@
+// Copyright 2023 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
+//
+// Licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf_gpio.h"
+#include "nrfx_uarte.h"
+
+// UART instance
+#ifdef USE_UART0
+nrfx_uarte_t uarte = NRFX_UARTE_INSTANCE(0);
+#endif
+
+void clock_setup(void) {}
+
+void usart_setup(void) {
+#ifdef USE_UART0
+  // Configuration for UARTE
+  const nrfx_uarte_config_t uarte_config = {
+      .txd_pin = NRF_GPIO_PIN_MAP(1, 1),
+      .rxd_pin = NRF_GPIO_PIN_MAP(1, 0),
+      .rts_pin = NRF_UARTE_PSEL_DISCONNECTED,
+      .cts_pin = NRF_UARTE_PSEL_DISCONNECTED,
+      .baudrate = UARTE_BAUDRATE_BAUDRATE_Baud115200,
+  };
+
+  // Enable UART
+  nrfx_uarte_init(&uarte, &uarte_config, NULL);
+#endif
+}
+
+void gpio_setup(void) {}
+
+void send_blocking(uint16_t c) {
+#ifdef USE_UART0
+  nrfx_uarte_tx(&uarte, (uint8_t*)&c, 1, NRFX_UARTE_TX_BLOCKING);
+#endif
+}
+
+bool wait_until(uint64_t nanos) { return true; }