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update REAMDE and add register address for SPI1, I2C1, GPIOA #30

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Aug 4, 2024
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update REAMDE and add register address for SPI1, I2C1, GPIOA #30

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22 changes: 11 additions & 11 deletions README.md
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Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
# STM32L432_FlashMaster

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STM32L432_FlashMaster is a baremetal project that uses the STM32L432KC microcontroller. Its purpose is to communicate with the IS25LP128F flash chip through SPI.
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43 changes: 43 additions & 0 deletions Src/Mcal/Reg.h
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Expand Up @@ -31,7 +31,12 @@
#define RCC_BASE 0x40021000UL
#define PWR_BASE 0x40007000UL
#define FLASH_BASE 0x40022000UL
#define GPIOA_BASE 0x48000000UL
#define GPIOB_BASE 0x48000400UL
#define I2C1_BASE 0x40005400UL
#define SPI1_BASE 0x40013000UL



/* FLASH registers */
#define FLASH_ACR (*(volatile uint32_t*)(FLASH_BASE + 0x000UL))
Expand All @@ -52,6 +57,16 @@
#define RCC_APB1ENR2 (*(volatile uint32_t*)(RCC_BASE + 0x5CUL))
#define RCC_APB2ENR (*(volatile uint32_t*)(RCC_BASE + 0x60UL))


/* GPIOA registers */
#define GPIOA_MODER (*(volatile uint32_t*)(GPIOA_BASE + 0x00UL))
#define GPIOA_OTYPER (*(volatile uint32_t*)(GPIOA_BASE + 0x04UL))
#define GPIOA_OSPEEDR (*(volatile uint32_t*)(GPIOA_BASE + 0x08UL))
#define GPIOA_PUPDR (*(volatile uint32_t*)(GPIOA_BASE + 0x0CUL))
#define GPIOA_ODR (*(volatile uint32_t*)(GPIOA_BASE + 0x14UL))
#define GPIOA_AFRL (*(volatile uint32_t*)(GPIOA_BASE + 0x20UL))
#define GPIOA_AFRH (*(volatile uint32_t*)(GPIOA_BASE + 0x24UL))

/* GPIOB registers */
#define GPIOB_MODER (*(volatile uint32_t*)(GPIOB_BASE + 0x00UL))
#define GPIOB_OTYPER (*(volatile uint32_t*)(GPIOB_BASE + 0x04UL))
Expand All @@ -61,6 +76,34 @@
#define GPIOB_AFRL (*(volatile uint32_t*)(GPIOB_BASE + 0x20UL))
#define GPIOB_AFRH (*(volatile uint32_t*)(GPIOB_BASE + 0x24UL))

/* I2C1 registers */
#define I2C1_CR1 (*(volatile uint32_t*)(I2C1_BASE + 0x00UL))
#define I2C1_CR2 (*(volatile uint32_t*)(I2C1_BASE + 0x04UL))
#define I2C1_OAR1 (*(volatile uint32_t*)(I2C1_BASE + 0x08UL))
#define I2C1_OAR2 (*(volatile uint32_t*)(I2C1_BASE + 0x0CUL))
#define I2C1_TIMINGR (*(volatile uint32_t*)(I2C1_BASE + 0x10UL))
#define I2C1_TIMEOUTR (*(volatile uint32_t*)(I2C1_BASE + 0x14UL))
#define I2C1_ISR (*(volatile uint32_t*)(I2C1_BASE + 0x18UL))
#define I2C1_ICR (*(volatile uint32_t*)(I2C1_BASE + 0x1CUL))
#define I2C1_PECR (*(volatile uint32_t*)(I2C1_BASE + 0x20UL))
#define I2C1_RXDR (*(volatile uint32_t*)(I2C1_BASE + 0x24UL))
#define I2C1_TXDR (*(volatile uint32_t*)(I2C1_BASE + 0x28UL))

/* SPI1 registers */
#define SPI1_CR1 (*(volatile uint32_t*)(SPI1_BASE + 0x00UL))
#define SPI1_CR2 (*(volatile uint32_t*)(SPI1_BASE + 0x04UL))
#define SPI1_SR (*(volatile uint32_t*)(SPI1_BASE + 0x08UL))
#define SPI1_DR (*(volatile uint16_t*)(SPI1_BASE + 0x0CUL))
#define SPI1_CRCPR (*(volatile uint32_t*)(SPI1_BASE + 0x10UL))
#define SPI1_RXCRCR (*(volatile uint32_t*)(SPI1_BASE + 0x14UL))
#define SPI1_TXCRCR (*(volatile uint32_t*)(SPI1_BASE + 0x18UL))









#endif /* REG_2023_08_26_H */
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