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v0.22: Many small improvements.
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@hneemann hneemann released this 01 Apr 07:42
v0.22
71be07a 
- Improved the RAM/ROM data loader. Now binary files and Intel HEX files
  are supported.
- Added a RAM that can be synthesized on an FPGA using block RAM.
- Now its possible to create circuits using lookup tables.
- More consistent handling of the initial state in the FSM editor.
- Added a rectangle to visually group elements.
- Added a MIDI component.
- The line number and the context from the test case description is shown
  in test result table.
- Added Portuguese translation. Special thanks to Theldo Cruz Franqueira
  who provided the translation.
- Breaking changes:
  - The timing of the EEPROM with a single data port has changed.
    See help text for details.
  - The timing of the RAM with Chip Select has changed.
    See help text for details.
Assets 6
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