Reset rb_i for each block is active low
clk_i is 50Mhz
Always follow names of inputs and outputs of blocks from blockdiagram
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Top Entity (UARTrx)
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Top Entity testbench
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D flip flop (dff)
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D flip flop test bench
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Divide by six (div6)
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Divide by six testbench
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Divide by 25 mega (div50meg)
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Divide by 25 mega testbench
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Parity Generator (pargen)
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Parity Generator testbench
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Shift register (shiftreg)
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Shift register testbench
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Sample timing and start bit FSM (FSM)
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Sample timing and start bit FSM testbench
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8 bit compare (eightcomp)
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8 bit compare testbench
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ROM (rom)
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ROM testbench
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1 bit compare (xnoren)
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1 bit compare testbench