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FPGA project that receives a password via UART serial and opens a door.

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hallmar/UART_RX

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UART_RX

Block diagram

Design rules

Reset rb_i for each block is active low

clk_i is 50Mhz

Always follow names of inputs and outputs of blocks from blockdiagram

Checklist

  • Top Entity (UARTrx)

  • Top Entity testbench

  • D flip flop (dff)

  • D flip flop test bench

  • Divide by six (div6)

  • Divide by six testbench

  • Divide by 25 mega (div50meg)

  • Divide by 25 mega testbench

  • Parity Generator (pargen)

  • Parity Generator testbench

  • Shift register (shiftreg)

  • Shift register testbench

  • Sample timing and start bit FSM (FSM)

  • Sample timing and start bit FSM testbench

  • 8 bit compare (eightcomp)

  • 8 bit compare testbench

  • ROM (rom)

  • ROM testbench

  • 1 bit compare (xnoren)

  • 1 bit compare testbench

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FPGA project that receives a password via UART serial and opens a door.

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