Support internal C>>17/PCIN>>17 feature on Xilinx DSPs

architecture_descriptions/xilinx_ultrascale_plus.yml

@@ -164,7 +164,8 @@ implementations:
       # connectivity or OPMODE value to allow for proper implementation.
       #
       # TODO(@gussmith23): deal with this when we support multiple DSPs.
-      "(not (bveq (extract 5 4 OPMODE) (bv #b01 2)))",
+      # This is the line that we need to get rid of to use PCIN.
+      # "(not (bveq (extract 5 4 OPMODE) (bv #b01 2)))",
 
       # ERROR: [DRC DSPS-4] Invalid PCIN Connection for CARRYINSEL value: DSP48E2 cell DSP48E2_0
       # has CARRYINSEL[2:0] set to 011 which uses the input of the PCIN bus for its computation,
@@ -250,7 +251,7 @@ implementations:
             { name: INMODE, direction: input, bitwidth: 5, value: INMODE },
             { name: MULTSIGNIN, direction: input, bitwidth: 1, value: (bv 0 1) },
             { name: OPMODE, direction: input, bitwidth: 9, value: OPMODE },
-            { name: PCIN, direction: input, bitwidth: 48, value: (bv 0 48) },
+            { name: PCIN, direction: input, bitwidth: 48, value: (choose (zero-extend C (bitvector 48)) (bv 0 48)) },
             { name: RSTA, direction: input, bitwidth: 1, value: (bv 0 1) },
             { name: RSTALLCARRYIN, direction: input, bitwidth: 1, value: (bv 0 1) },
             { name: RSTALUMODE, direction: input, bitwidth: 1, value: (bv 0 1) },

integration_tests/lakeroad/xilinx_ultrascale_plus_mac_with_internal_shift.v

@@ -0,0 +1,46 @@
+// RUN: outfile=$(mktemp)
+// RUN: racket $LAKEROAD_DIR/bin/main.rkt \
+// RUN:  --solver bitwuzla \
+// RUN:  --verilog-module-filepath %s \
+// RUN:  --architecture xilinx-ultrascale-plus \
+// RUN:  --template dsp \
+// RUN:  --out-format verilog \
+// RUN:  --top-module-name top \
+// RUN:  --verilog-module-out-signal out:48 \
+// RUN:  --pipeline-depth 0 \
+// RUN:  --module-name out \
+// RUN:  --input-signal 'c:(port c 47):47' \
+// RUN:  --timeout 90 \
+// RUN: > $outfile
+// RUN: FileCheck %s < $outfile
+// RUN: if [ -z ${LAKEROAD_PRIVATE_DIR+x} ]; then \
+// RUN:   echo "Warning: LAKEROAD_PRIVATE_DIR is not set. Skipping simulation."; \
+// RUN:   exit 0; \
+// RUN: else \
+// RUN:   python3 $LAKEROAD_DIR/bin/simulate_with_verilator.py \
+// RUN:    --test_module_name out \
+// RUN:    --ground_truth_module_name top \
+// RUN:    --max_num_tests=10000 \
+// RUN:    --verilog_filepath $outfile \
+// RUN:    --verilog_filepath %s \
+// RUN:    --pipeline_depth 0 \
+// RUN:    --output_signal out:48 \
+// RUN:    --input_signal c:47 \
+// RUN:    --verilator_include_dir "$LAKEROAD_PRIVATE_DIR/DSP48E2/" \
+// RUN:    --verilator_extra_arg='-DXIL_XECLIB' \
+// RUN:    --verilator_extra_arg='-Wno-UNOPTFLAT' \
+// RUN:    --verilator_extra_arg='-Wno-LATCH' \
+// RUN:    --verilator_extra_arg='-Wno-WIDTH' \
+// RUN:    --verilator_extra_arg='-Wno-STMTDLY' \
+// RUN:    --verilator_extra_arg='-Wno-CASEX' \
+// RUN:    --verilator_extra_arg='-Wno-TIMESCALEMOD' \
+// RUN:    --verilator_extra_arg='-Wno-PINMISSING'; \
+// RUN: fi
+
+// TODO(@gussmith23): For some reason, this doesn't work with c of length 48.
+// Works with 47 though.
+module top(input [46:0] c, output [47:0] out);
+  assign out = 48'(48'(c) >> 17);
+endmodule
+
+// CHECK: module out(c, out);

integration_tests/lakeroad/xilinx_ultrascale_plus_mac_with_internal_shift_broken.v

@@ -0,0 +1,48 @@
+// RUN: outfile=$(mktemp)
+// RUN: (racket $LAKEROAD_DIR/bin/main.rkt \
+// RUN:  --solver bitwuzla \
+// RUN:  --verilog-module-filepath %s \
+// RUN:  --architecture xilinx-ultrascale-plus \
+// RUN:  --template dsp \
+// RUN:  --out-format verilog \
+// RUN:  --top-module-name top \
+// RUN:  --verilog-module-out-signal out:48 \
+// RUN:  --pipeline-depth 0 \
+// RUN:  --module-name out \
+// RUN:  --input-signal 'c:(port c 48):48' \
+// RUN:  --timeout 90 \
+// RUN:  || true) \
+// RUN:  > $outfile \
+// RUN:  2>&1
+// RUN: FileCheck %s < $outfile
+// if [ -z ${LAKEROAD_PRIVATE_DIR+x} ]; then \
+//   echo "Warning: LAKEROAD_PRIVATE_DIR is not set. Skipping simulation."; \
+//   exit 0; \
+// else \
+//   python3 $LAKEROAD_DIR/bin/simulate_with_verilator.py \
+//    --test_module_name out \
+//    --ground_truth_module_name top \
+//    --max_num_tests=10000 \
+//    --verilog_filepath $outfile \
+//    --verilog_filepath %s \
+//    --pipeline_depth 0 \
+//    --output_signal out:48 \
+//    --input_signal c:47 \
+//    --verilator_include_dir "$LAKEROAD_PRIVATE_DIR/DSP48E2/" \
+//    --verilator_extra_arg='-DXIL_XECLIB' \
+//    --verilator_extra_arg='-Wno-UNOPTFLAT' \
+//    --verilator_extra_arg='-Wno-LATCH' \
+//    --verilator_extra_arg='-Wno-WIDTH' \
+//    --verilator_extra_arg='-Wno-STMTDLY' \
+//    --verilator_extra_arg='-Wno-CASEX' \
+//    --verilator_extra_arg='-Wno-TIMESCALEMOD' \
+//    --verilator_extra_arg='-Wno-PINMISSING'; \
+// fi
+
+// TODO(@gussmith23): For some reason, this doesn't work with c of length 48.
+// Works with 47 though.
+module top(input [47:0] c, output [47:0] out);
+  assign out = 48'(48'(c) >> 17);
+endmodule
+
+// CHECK: Synthesis failed