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Add mainline kernel device tree support
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Enabling the mainline kernel support also generate the fixed clocks for
the peripherals.

Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Acked-by: Michal Simek <[email protected]>
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Venkatesh Yadav Abbarapu committed Jul 2, 2018
1 parent 839dc9f commit fde2eb7
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Showing 10 changed files with 265 additions and 115 deletions.
13 changes: 8 additions & 5 deletions ams/data/ams.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -20,10 +20,13 @@ proc generate {drv_handle} {
break
}
}
set ams_list "ams_ps ams_pl"
set dts_file [get_property CONFIG.pcw_dts [get_os]]
foreach ams_name ${ams_list} {
set ams_node [add_or_get_dt_node -n "&${ams_name}" -d $dts_file]
hsi::utils::add_new_dts_param "${ams_node}" "status" "okay" string
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set ams_list "ams_ps ams_pl"
set dts_file [get_property CONFIG.pcw_dts [get_os]]
foreach ams_name ${ams_list} {
set ams_node [add_or_get_dt_node -n "&${ams_name}" -d $dts_file]
hsi::utils::add_new_dts_param "${ams_node}" "status" "okay" string
}
}
}
31 changes: 18 additions & 13 deletions axi_cdma/data/axi_cdma.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -45,19 +45,24 @@ proc generate {drv_handle} {
set tx_chan [add_dma_channel $drv_handle $node "axi-cdma" $baseaddr "MM2S" $cdma_count ]
incr cdma_count
hsi::utils::set_os_parameter_value "cdma_count" $cdma_count
set proc_type [get_sw_proc_prop IP_NAME]
switch $proc_type {
"psu_cortexa53" {
update_clk_node $drv_handle "s_axi_lite_aclk m_axi_aclk"
} "ps7_cortexa9" {
update_zynq_clk_node $drv_handle "s_axi_lite_aclk m_axi_aclk"
} "microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk"
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
}
default {
error "Unknown arch"
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set proc_type [get_sw_proc_prop IP_NAME]
switch $proc_type {
"psu_cortexa53" {
update_clk_node $drv_handle "s_axi_lite_aclk m_axi_aclk"
} "ps7_cortexa9" {
update_zynq_clk_node $drv_handle "s_axi_lite_aclk m_axi_aclk"
} "microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk"
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
}
default {
error "Unknown arch"
}
}
} else {
generate_clk_nodes $drv_handle
}
}

Expand Down Expand Up @@ -113,7 +118,7 @@ proc generate_clk_nodes {drv_handle} {
hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int
hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int
set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]
set_drv_prop_if_empty $drv_handle "clocks" "$clk_refs &$clk_refs" reference
set_drv_prop_if_empty $drv_handle "clocks" "$clk_refs>, <&$clk_refs" reference
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
} "microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk"
Expand Down
124 changes: 95 additions & 29 deletions axi_dma/data/axi_dma.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -101,26 +101,30 @@ proc generate {drv_handle} {
}
incr dma_count
hsi::utils::set_os_parameter_value "dma_count" $dma_count
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
}
set clkname_len [llength $clocknames]
if {[string match -nocase $proc_type "psu_cortexa53"]} {
update_clk_node $drv_handle $clocknames $clkname_len
} elseif {[string match -nocase $proc_type "ps7_cortexa9"]} {
update_zynq_clk_node $drv_handle $clocknames $clkname_len
} elseif {[string match -nocase $proc_type "microblaze"]} {
generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
}
set clkname_len [llength $clocknames]
if {[string match -nocase $proc_type "psu_cortexa53"]} {
update_clk_node $drv_handle $clocknames $clkname_len
} elseif {[string match -nocase $proc_type "ps7_cortexa9"]} {
update_zynq_clk_node $drv_handle $clocknames $clkname_len
} elseif {[string match -nocase $proc_type "microblaze"]} {
generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan
}
} else {
generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan
}

}

proc add_dma_channel {drv_handle parent_node xdma addr mode devid} {
Expand Down Expand Up @@ -173,18 +177,80 @@ proc add_dma_coherent_prop {drv_handle intf} {
}

proc generate_clk_nodes {drv_handle axiethernetfound tx_chan rx_chan} {
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
switch $proc_type {
"ps7_cortexa9" {
set clocks "clkc 15"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
append clocks "" ">, <&clkc 15"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocks "" ">, <&clkc 15"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocks "" ">, <&clkc 15"
}
set_drv_prop_if_empty $drv_handle "clocks" $clocks reference
set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist
} "psu_cortexa53" {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"]
if {![string equal $clk_freq ""]} {
if {[lsearch $bus_clk_list $clk_freq] < 0} {
set bus_clk_list [lappend bus_clk_list $clk_freq]
}
}
set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]
set dts_file [current_dt_tree]
set bus_node [add_or_get_bus_node $drv_handle $dts_file]
set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \
-d ${dts_file} -p ${bus_node}]
hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist
hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int
hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int
set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]
set clocks "$clk_refs"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
append clocks "" ">, <&$clk_refs"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocks "" ">, <&$clk_refs"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocks "" ">, <&$clk_refs"
}
set_drv_prop_if_empty $drv_handle "clocks" "$clocks" reference
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
} "microblaze" {
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
}
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
}
default {
error "Unknown arch"
}
}
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
}

proc get_connected_ip {drv_handle dma_pin} {
Expand Down
48 changes: 26 additions & 22 deletions axi_vdma/data/axi_vdma.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -85,30 +85,34 @@ proc generate {drv_handle} {
}
incr vdma_count
hsi::utils::set_os_parameter_value "vdma_count" $vdma_count
generate_clk_nodes $drv_handle $tx_chan $rx_chan
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocknames " " "m_axi_s2mm_aclk"
}
set clkname_len [llength $clocknames]
switch $proc_type {
"psu_cortexa53" {
update_clk_node $drv_handle $clocknames $clkname_len
} "ps7_cortexa9" {
update_zynq_clk_node $drv_handle $clocknames $clkname_len
} "microblaze" {
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocknames " " "m_axi_s2mm_aclk"
}
default {
error "Unknown arch"
set clkname_len [llength $clocknames]
switch $proc_type {
"psu_cortexa53" {
update_clk_node $drv_handle $clocknames $clkname_len
} "ps7_cortexa9" {
update_zynq_clk_node $drv_handle $clocknames $clkname_len
} "microblaze" {
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
}
default {
error "Unknown arch"
}
}
} else {
generate_clk_nodes $drv_handle $tx_chan $rx_chan
}
}

Expand Down
8 changes: 6 additions & 2 deletions cpu_cortexa53/data/cpu_cortexa53.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,12 @@

proc generate {drv_handle} {
global dtsi_fname
set dtsi_fname "zynqmp/zynqmp.dtsi"

set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase "$mainline_ker" "v4.17"]} {
set dtsi_fname "zynqmp/zynqmp.dtsi"
} else {
set dtsi_fname "zynqmp/zynqmp.dtsi"
}
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
Expand Down
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