This is a Python script designed to read HDL files and lock the design using a variety of user-selectable locking methods. It outputs a new Verilog file which can be flashed to an FPGA.
Designed by the UNCC FLOW Senior Design project team.
Run the script with Python3:
python3 automation.py -step <step> -method <method> <project path>
W. Halaburda and G. Briceno and W. Obey and N. N. BouSaba and F. Saqib, "A Novel User-Friendly Automated Framework for FPGA Design Logic Encryption," in 2020 IEEE 17th International Conference on Smart Communities: Improving Quality of Life Using ICT, IoT and AI, HONET 2020, Charlotte, NC USA, December 14, 2020, pp. 241-243.