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HIP: Enable Matrix cores for MMQ Kernels, Enable stream-K for CDNA 3 #14624
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68da4e5
Feat: Enable MFMA instr for Q4_K
deepsek 79f348a
Fix: Missed template param
deepsek 89ba8a6
Feat: Add MFMA instr for Q6_K, remove MMQ_NWARPS
deepsek e57e563
Merge branch 'ggml-org:master' into amd-integration
deepsek 9784a51
Merge branch 'ggml-org:master' into amd-integration
deepsek dad79b3
Merge branch 'ggml-org:master' into amd-integration
deepsek ff60fa9
Perf: Fix Register Spilling Q6_K - Refactor kernel, launch_bound
deepsek e8eeb34
Perf: Refactor Q4_K, reduce register pressure
deepsek a161900
Perf: Throughput Increase 4k->6.9k t/s
deepsek 75d386a
Perf: 7.1k tokens/sec
deepsek 0215a80
Perf/Feat: Throughput 8.3k tokens/sec, Add support for all quants
deepsek aa35feb
Feat: Remove warnings, deprecated __AMDGCN_WAVEFRONT_SIZE
deepsek ba17f62
Merge branch 'master' into amd-integration
deepsek 5ab1491
Feat: Enable stream-k for CDNA3
deepsek fb2fd31
Fix: Remove Trailing Whitespaces
deepsek b55d44a
Fix: Unused Params Warnings, CUDA Build
deepsek ab7c007
-p512: 8.4k->9.5k - Account for DataPadding for writing tile_y
deepsek 279b51e
refactor: PR code cleanup, amd_mma_available->amd_mfma_available
deepsek a2a336b
refactor: PR cleanup
deepsek b489b4e
Feat/Perf: redesign all quants use same tile size, mfma instr, nwarps
deepsek 4e6d54f
Fix: CI fail - unused parameter Werror
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I think this would be simpler.
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Do you mean without the preprocessor directives?
This would affect the NV code path when we call load_generic though? I see some instances where load_generic is called
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I basically meant to have the instructions for loading data as 64 bit encapsulated in an
ifdef AMD_MFMA_AVAILABLE ... #endif
and to use the generic implementation if the preconditions aren't met. But if this is going to be refactored anyways it doesn't matter.