Fix deprecated warnings

freechipsproject · Nov 17, 2022 · e245f60 · e245f60
1 parent de4f769
commit e245f60
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Showing 5 changed files with 19 additions and 19 deletions.
diff --git a/build.sbt b/build.sbt
@@ -34,17 +34,17 @@ lazy val root = (project in file("."))
     name := "ip-contributions",
     resolvers += Resolver.sonatypeRepo("snapshots"),
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chisel3" % "3.5.4",
-      "edu.berkeley.cs" %% "dsptools" % "1.5.4",
-      "edu.berkeley.cs" %% "chiseltest" % "0.5.4" % "test",
+      "edu.berkeley.cs" %% "chisel3" % "3.5.5",
+      "edu.berkeley.cs" %% "dsptools" % "1.5.5",
+      "edu.berkeley.cs" %% "chiseltest" % "0.5.5" % "test",
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",
       "-deprecation",
       "-feature",
       "-Xcheckinit",
     ),
-    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.4" cross CrossVersion.full),
+    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.5" cross CrossVersion.full),
     addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
   )
   .settings(publishSettings: _*)
diff --git a/src/main/scala/chisel/lib/cordic/iterative/Cordic.scala b/src/main/scala/chisel/lib/cordic/iterative/Cordic.scala
@@ -152,7 +152,7 @@ class IterativeCordic[T <: Data: Real: BinaryRepresentation](val params: CordicP
   io.out.valid := outValid
 
   // when the input interface turns valid deassert ready & load the initial data (incl. initial rotation if necessary)
-  when(io.in.fire()) {
+  when(io.in.fire) {
     inReady := false.B
     vecReg := io.in.bits.vectoring
     extReg := ext
@@ -174,7 +174,7 @@ class IterativeCordic[T <: Data: Real: BinaryRepresentation](val params: CordicP
   when(counter >= (params.nStages).U) {
     outValid := true.B
 
-    when(io.out.fire()) {
+    when(io.out.fire) {
       counter := 0.U
       inReady := true.B
       outValid := false.B

diff --git a/src/main/scala/chisel/lib/dclib/DCCredit.scala b/src/main/scala/chisel/lib/dclib/DCCredit.scala
@@ -24,15 +24,15 @@ class DCCreditSender[D <: Data](data: D, maxCredit: Int) extends Module {
   require(maxCredit >= 1)
 
   val icredit = RegNext(io.deq.credit)
-  val curCredit = RegInit(init = maxCredit.U)
-  when(icredit && !io.enq.fire()) {
+  val curCredit = RegInit(maxCredit.U)
+  when(icredit && !io.enq.fire) {
     curCredit := curCredit + 1.U
-  }.elsewhen(!icredit && io.enq.fire()) {
+  }.elsewhen(!icredit && io.enq.fire) {
     curCredit := curCredit - 1.U
   }
   io.enq.ready := curCredit > 0.U
-  val dataOut = RegEnable(next = io.enq.bits, enable = io.enq.fire())
-  val validOut = RegNext(next = io.enq.fire(), init = false.B)
+  val dataOut = RegEnable(io.enq.bits, io.enq.fire)
+  val validOut = RegNext(io.enq.fire, false.B)
   io.deq.valid := validOut
   io.deq.bits := dataOut
   io.curCredit := curCredit
@@ -53,6 +53,6 @@ class DCCreditReceiver[D <: Data](data: D, maxCredit: Int) extends Module {
   outFifo.io.enq.bits := idata
   io.fifoCount := outFifo.io.count
   io.deq <> outFifo.io.deq
-  val ocredit = RegNext(next = outFifo.io.deq.fire(), init = false.B)
+  val ocredit = RegNext(outFifo.io.deq.fire, false.B)
   io.enq.credit := ocredit
 }
diff --git a/src/main/scala/chisel/lib/dclib/DCOutput.scala b/src/main/scala/chisel/lib/dclib/DCOutput.scala
@@ -17,8 +17,8 @@ class DCOutput[D <: Data](data: D) extends Module {
   val r_valid = RegInit(false.B)
 
   io.enq.ready := io.deq.ready || !r_valid
-  r_valid := io.enq.fire() || (r_valid && !io.deq.ready)
-  io.deq.bits := RegEnable(next = io.enq.bits, enable = io.enq.fire())
+  r_valid := io.enq.fire || (r_valid && !io.deq.ready)
+  io.deq.bits := RegEnable(io.enq.bits, io.enq.fire)
   io.deq.valid := r_valid
 }
 

diff --git a/src/test/scala/chisel/lib/dclib/ColorSource.scala b/src/test/scala/chisel/lib/dclib/ColorSource.scala
@@ -26,7 +26,7 @@ class ColorSource(colors: Int, dsz: Int) extends Module {
   val seqnum = RegInit(0.asUInt(dsz.W))
   val strobe = RegInit(0.asUInt(4.W))
 
-  when(io.p.fire()) {
+  when(io.p.fire) {
     seqnum := seqnum + 1.U
   }
 
@@ -62,7 +62,7 @@ class ColorSink(colors: Int, dsz: Int) extends Module {
   val color_error = RegInit(false.B)
   val okCount = RegInit(0.U(32.W))
 
-  when(io.c.fire()) {
+  when(io.c.fire) {
     seqnum := seqnum + 1.U
     when(io.c.bits.seqnum =/= seqnum) {
       seq_error := true.B
@@ -120,7 +120,7 @@ class PktTokenSource(asz: Int, cycsz: Int = 16, id: Int = 0) extends Module {
   cycle := cycle + 1.U
   io.cum_delay := cum_delay
 
-  when(io.p.fire() || !io.pattern(strobe)) {
+  when(io.p.fire || !io.pattern(strobe)) {
     strobe := strobe + 1.U
   }
   ohold.io.enq.valid := io.pattern(strobe)
@@ -156,11 +156,11 @@ class PktTokenSink(asz: Int, cycsz: Int = 16, id: Int = 0) extends Module {
   cycle := cycle + 1.U
 
   c_hold.ready := io.pattern(strobe)
-  when(c_hold.fire() || !io.pattern(strobe)) {
+  when(c_hold.fire || !io.pattern(strobe)) {
     strobe := strobe + 1.U
   }
 
-  when(c_hold.fire()) {
+  when(c_hold.fire) {
     cum_latency := cum_latency + (cycle - c_hold.bits.cycle)
     pkt_count := pkt_count + 1.U
     when(c_hold.bits.dst =/= id.U) {