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feat(esp32c5): add target esp32c5 beta3
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ROM version: 20230803
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L-KAYA committed Jan 2, 2024
1 parent 8538b89 commit d9a6660
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Showing 18 changed files with 1,750 additions and 14 deletions.
4 changes: 4 additions & 0 deletions espefuse/__init__.py
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import espefuse.efuse.esp32 as esp32_efuse
import espefuse.efuse.esp32c2 as esp32c2_efuse
import espefuse.efuse.esp32c3 as esp32c3_efuse
import espefuse.efuse.esp32c5beta3 as esp32c5beta3_efuse
import espefuse.efuse.esp32c6 as esp32c6_efuse
import espefuse.efuse.esp32h2 as esp32h2_efuse
import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse
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"esp32c2": DefChip("ESP32-C2", esp32c2_efuse, esptool.targets.ESP32C2ROM),
"esp32c3": DefChip("ESP32-C3", esp32c3_efuse, esptool.targets.ESP32C3ROM),
"esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM),
"esp32c5beta3": DefChip(
"ESP32-C5(beta3)", esp32c5beta3_efuse, esptool.targets.ESP32C5BETA3ROM
),
"esp32h2": DefChip("ESP32-H2", esp32h2_efuse, esptool.targets.ESP32H2ROM),
"esp32p4": DefChip("ESP32-P4", esp32p4_efuse, esptool.targets.ESP32P4ROM),
"esp32h2beta1": DefChip(
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3 changes: 3 additions & 0 deletions espefuse/efuse/esp32c5beta3/__init__.py
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from . import operations
from .emulate_efuse_controller import EmulateEfuseController
from .fields import EspEfuses
92 changes: 92 additions & 0 deletions espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py
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# This file describes eFuses controller for ESP32-C5 beta3 chip
#
# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: GPL-2.0-or-later

import reedsolo

from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters
from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError


class EmulateEfuseController(EmulateEfuseControllerBase):
"""The class for virtual efuse operation. Using for HOST_TEST."""

CHIP_NAME = "ESP32-C5(beta3)"
mem = None
debug = False

def __init__(self, efuse_file=None, debug=False):
self.Blocks = EfuseDefineBlocks
self.Fields = EfuseDefineFields()
self.REGS = EfuseDefineRegisters
super(EmulateEfuseController, self).__init__(efuse_file, debug)
self.write_reg(self.REGS.EFUSE_CMD_REG, 0)

""" esptool method start >>"""

def get_major_chip_version(self):
return 0

def get_minor_chip_version(self):
return 0

def get_crystal_freq(self):
return 40 # MHz (common for all chips)

def get_security_info(self):
return {
"flags": 0,
"flash_crypt_cnt": 0,
"key_purposes": 0,
"chip_id": 0,
"api_version": 0,
}

""" << esptool method end """

def handle_writing_event(self, addr, value):
if addr == self.REGS.EFUSE_CMD_REG:
if value & self.REGS.EFUSE_PGM_CMD:
self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF)
self.clean_blocks_wr_regs()
self.check_rd_protection_area()
self.write_reg(addr, 0)
self.write_reg(self.REGS.EFUSE_CMD_REG, 0)
elif value == self.REGS.EFUSE_READ_CMD:
self.write_reg(addr, 0)
self.write_reg(self.REGS.EFUSE_CMD_REG, 0)
self.save_to_file()

def get_bitlen_of_block(self, blk, wr=False):
if blk.id == 0:
if wr:
return 32 * 8
else:
return 32 * blk.len
else:
if wr:
rs_coding = 32 * 3
return 32 * 8 + rs_coding
else:
return 32 * blk.len

def handle_coding_scheme(self, blk, data):
if blk.id != 0:
# CODING_SCHEME RS applied only for all blocks except BLK0.
coded_bytes = 12
data.pos = coded_bytes * 8
plain_data = data.readlist("32*uint:8")[::-1]
# takes 32 bytes
# apply RS encoding
rs = reedsolo.RSCodec(coded_bytes)
# 32 byte of data + 12 bytes RS
calc_encoded_data = list(rs.encode([x for x in plain_data]))
data.pos = 0
if calc_encoded_data != data.readlist("44*uint:8")[::-1]:
raise FatalError("Error in coding scheme data")
data = data[coded_bytes * 8 :]
if blk.len < 8:
data = data[(8 - blk.len) * 32 :]
return data
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