Verified nested IRQ handling on S32Z280 silicon

[fdesbiens]

#611 exercised the nesting routines on the FVP and established what breaks them:
the interrupt must be acknowledged before nesting starts, or the still-pending
level-asserted timer is retaken the moment IRQ is enabled and recurses until the
stacks are gone. entry.S here carries the same ordering for the same reason, and
irq_dispatch.c splits the same way — board_irq_service takes an
already-acknowledged INTID while board_irq_handler keeps its old shape as the
non-nesting entry point.

What the model could not answer is whether a real GIC-600 agrees. Two things could
have differed, and both are now checked rather than hoped for.

Implemented priority bits. Equal priorities do not preempt, and it is the low
bits that vanish — so if the timer and the SGI collapse to a single value after
truncation, nesting cannot happen at all, and the test would fail without saying
why. gicv3_priority_bits discovers the count by writing 0xFF to a priority
byte and reading back which bits stick; board_init records the two effective
values; check P1 requires the SGI to still outrank the timer. This silicon
keeps five bits, the same as the FVP, so 0xA0 and 0x50 stay distinct. That is
now measured and reported instead of assumed.

SGI delivery on real hardware. ICC_SGI1R is a 64-bit AArch32 CP15 register
whose encoding does not transcribe from the AArch64 alias, so check N1 raises
one from thread context and requires delivery before nesting is involved. It
arrives.

Verified on silicon

priority bits   = 0x00000005
timer effective = 0x000000A0    sgi effective = 0x00000050
P1 SGI outranks timer after truncation     PASS
N1 SGI delivered and dispatched            PASS
max depth = 0x00000002   nested SGIs = 0x00000032   depth now = 0x00000000
N2 SGI nested inside another handler       PASS
N3 nesting unwound to depth zero           PASS
N4 tick still advancing after nesting      PASS
N5 lower-priority thread still scheduled   PASS
N6 no spurious or unexpected interrupts    PASS
PASS nested IRQ handling verified on silicon

Fifty nested SGIs across fifty ticks — one per tick — and depth never exceeded
two.

No regression, checked both ways on the board

• Nesting build: the ThreadX demo still reports 100 ticks with 20 preemptions,
  and the boot image still passes its cache (C3/C4) and protection (X2/X4) checks.
• Default build: the image links zero irq_nesting symbols, and the demo
  is unchanged. That is the configuration everyone ships, so it is worth showing
  the nesting work is genuinely absent from it rather than merely inactive.

Both toolchains compile every file — GNU with no warnings, and Arm Toolchain for
Embedded 22.1.0.