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This PR contains the following updates:
0.10.1
->0.12.0
0.11.0
->0.13.0
Release Notes
rust-embedded/riscv (riscv)
v0.12.0
:riscv
0.12.0New features
riscv
0.12.0riscv-macros
for helping during the definition of custom interrupt and exception sourcesriscv-pac
0.2.0usize
numbersExceptionNumber
trait for custom exception numbersriscv-peripheral
0.2.0riscv-rt
0.13.0_dispatch_exception
function_dispatch_interrupt
functionno-exceptions
andno-interrupts
features. This way, you can adaptriscv-rt
to target-specific sources.pre_init_trap
to detect early errors during the boot process.v-trap
feature!core_interrupt
,external_interrupt
, andexception
macros for defining interrupt and exception handlersu-boot
feature to execute U-boot binaries.Configuration
📅 Schedule: Branch creation - At any time (no schedule defined), Automerge - At any time (no schedule defined).
🚦 Automerge: Disabled by config. Please merge this manually once you are satisfied.
♻ Rebasing: Whenever PR becomes conflicted, or you tick the rebase/retry checkbox.
👻 Immortal: This PR will be recreated if closed unmerged. Get config help if that's undesired.
This PR was generated by Mend Renovate. View the repository job log.