Merge pull request icl-utk-edu#202 from Treece-Burgess/libpfm4-update…

…-07-09-24

Update libpfm4 to commit 2bf0d4

src/libpfm4/README

@@ -43,6 +43,7 @@ The library supports many PMUs. The current version can handle:
 		AMD64 Fam17h (Zen2)
 		AMD64 Fam19h (Zen3) (core and L3)
 		AMD64 Fam19h (Zen4)
+		AMD64 Fam1Ah (Zen5) (core and L3)
 
 	- For Intel X86: 
 		Intel P6 (Pentium II, Pentium Pro, Pentium III, Pentium M)

src/libpfm4/docs/Makefile

@@ -47,6 +47,8 @@ ARCH_MAN=libpfm_intel_core.3	\
 	 libpfm_amd64_fam19h_zen3.3 \
 	 libpfm_amd64_fam19h_zen4.3 \
 	 libpfm_amd64_fam19h_zen3_l3.3 \
+	 libpfm_amd64_fam1ah_zen5.3  \
+	 libpfm_amd64_fam1ah_zen5_l3.3 \
 	 libpfm_intel_atom.3	\
 	 libpfm_intel_nhm.3	\
 	 libpfm_intel_nhm_unc.3 \

src/libpfm4/docs/man3/libpfm_amd64_fam1ah_zen5.3

@@ -0,0 +1,49 @@
+.TH LIBPFM 3  "May, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_amd64_fam1ah_zen5 - support for AMD64 Family 1Ah processors
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: amd64_fam1ah_zen5
+.B PMU desc: AMD64 Fam1Ah Zen5
+.sp
+.SH DESCRIPTION
+The library supports AMD Family 1Ah processors Zen5 core PMU in both 32 and 64-bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on AMD64 Family 1Ah Zen5 core PMU:
+.TP
+.B u
+Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B h
+Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR.
+This modifier is available starting with Fam10h. This is a boolean modifier.
+.TP
+.B g
+Measure at while executing in guest mode (when using virtualization). This modifier is available
+starting with Fam10h. This is a boolean modifier.
+.TP
+.B i
+Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR
+occurring. This is a boolean modifier
+.TP
+.B e
+Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier.
+.TP
+.B c
+Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles
+in which the number of occurrences of the event is greater or equal to the threshold. This is an integer
+modifier with values in the range [0:255].
+
+.SH AUTHORS
+.nf
+Swarup Sahoo
+.if
+.PP

src/libpfm4/docs/man3/libpfm_amd64_fam1ah_zen5_l3.3

@@ -0,0 +1,19 @@
+.TH LIBPFM 3  "May, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_amd64_fam1ah_zen5_l3 - support for AMD64 Family 1Ah L3 PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: amd64_fam1ah_zen5_l3
+.B PMU desc: AMD64 Fam1Ah Zen5 L3
+.sp
+.SH DESCRIPTION
+The library supports AMD Family 1Ah processors Zen5 L3 PMU in both 32 and 64-bit modes.
+
+At this point, there is no modifier supported.
+.SH AUTHORS
+.nf
+Swarup Sahoo
+.if
+.PP

src/libpfm4/include/perfmon/pfmlib.h

@@ -812,6 +812,8 @@ typedef enum {
 
 	PFM_PMU_INTEL_GNR,		/* Intel GraniteRapids core PMU */
 
+	PFM_PMU_AMD64_FAM1AH_ZEN5,      /* AMD64 Fam1Ah Zen5 */
+	PFM_PMU_AMD64_FAM1AH_ZEN5_L3,	/* AMD64 Fam1Ah Zen5 L3 */
 	/* MUST ADD NEW PMU MODELS HERE */
 
 	PFM_PMU_MAX			/* end marker */

src/libpfm4/lib/Makefile

@@ -146,7 +146,8 @@ SRCS   += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \
 	  pfmlib_amd64_fam14h.c pfmlib_amd64_fam15h.c \
 	  pfmlib_amd64_fam17h.c pfmlib_amd64_fam16h.c \
 	  pfmlib_amd64_fam19h.c pfmlib_amd64_rapl.c \
-	  pfmlib_amd64_fam19h_l3.c
+	  pfmlib_amd64_fam19h_l3.c \
+	  pfmlib_amd64_fam1ah.c pfmlib_amd64_fam1ah_l3.c
 
 CFLAGS += -DCONFIG_PFMLIB_ARCH_X86
 
@@ -280,6 +281,8 @@ INC_X86= pfmlib_intel_x86_priv.h	\
 	events/amd64_events_fam19h_zen4.h \
 	events/amd64_events_fam19h_zen3_l3.h \
 	events/amd64_events_fam16h.h	\
+	events/amd64_events_fam1ah_zen5.h    \
+	events/amd64_events_fam1ah_zen5_l3.h \
 	events/intel_p6_events.h	\
 	events/intel_netburst_events.h	\
 	events//intel_x86_arch_events.h \