Wire calculatePartialSums to native SIMD via Panama FFI downcall#651
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Wire calculatePartialSums to native SIMD via Panama FFI downcall#651
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added 2 commits
April 2, 2026 03:25
* Replace icelake-server gcc target with skylake-avx512 in build script * Remove global mutable state: eliminate initialIndexRegister, indexIncrement, maskSeventhBit, maskEighthBit globals and their constructor initializer; move mask constants (maskSeventhBit, maskEighthBit) to local scope inside lookup_partial_sums * Add shared reduce_add_128_ps and reduce_add_256_ps helper functions using proper horizontal-add sequences instead of store-to-array loops * Remove redundant if (length >= N) guards in all SIMD kernels — the loop body already handles the zero-iteration case correctly * Replace store-to-aligned-array horizontal reduction pattern with the new helpers across all 128- and 256-bit dot product and euclidean distance functions * Remove preferred_size parameter from dot_product_f32 and euclidean_f32; always dispatch to AVX-512 when length >= 16 * Standardize inline annotations: replace __attribute__((always_inline)) inline with JV_FINLINE / JV_INLINE macros throughout
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This change uses a native implementation of
calculatePartialSumsto accelerate PQ query scoring.On
ada002-100kwith FUSED_PQ (numPQsubspaces/M =96, JDK build 23.0.1+11-39), it delivers 2–3× higher QPS and 40–65% lower mean latency across common overquery settings. Index build time, disk usage, and heap usage show no meaningful regression. The optimization is isolated to the PQ path; non‑PQ queries are unaffected.Combined QPS and Latency Results (FUSED_PQ)
topK = 10
topK = 100
Summary of changes in this PR:
calculatePartialSumsin NativeVectorUtilSupport to a new Panama FFI downcall for the nativecalculate_partial_sums_f32_512SIMD implementation.