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QtRVSim version 0.9.4 release
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@ppisa ppisa released this 27 Oct 08:14
· 228 commits to master since this release
v0.9.4
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ppisa Pavel Pisa
GPG key ID: 868410FF2B4709CB
Learn about vigilant mode.
0d049e7
  • GUI: Async modal library to overcome WebAssembly/Emscripten limitations
  • Wasm: support and build improved
  • os_emulation: correct open flags O_xxx values to match RISC-V Linux ABI.
  • packaging: fix Fedora build according to Jan Grulich advice.
  • README.md: add reference to Embedded World Conference 2022 article.
  • qtrvsim_tester: Tomas Veznik implemented testing against official RISC/V ISA tests.
  • CI: speedup by using common build of official tests
  • Machine: initial support for CSR instructions by Jakub Dupak
  • GUI: CSR: syntax highlight CSR reg names
  • Machine: CSR: disassemble CSR register based on the mnemonic register settings
  • GUI: save mnemonic registers settings
  • Machine: add support for 64-bit RV64IM target and related 32-bit/word limited instructions
  • README.md: update information about basic 64-bit support.
  • Students work was funded by RPAPS 2022 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
  • We thanks for actual funding to Czech Technical University https://www.cvut.cz/

For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
Experimental Emscripten build can be accessed online https://comparch.edu.cvut.cz/qtrvsim/app

QtRvSim has been presented at Embedded World Conference 2022 in Session 10.3 – System-on-Chip (SoC) Design RISC-V Development https://events.weka-fachmedien.de/embedded-world-conference/
The presentation slides and related article QtRvSim – RISC-V Simulator for Computer Architectures Classes can be found on Computer Architectures courses materials page of the Czech Technical University in Prague https://comparch.edu.cvut.cz/

Upcoming presentation with live stream at DevConf CZ MINI https://www.devconf.info/cz/
QtRVSim – RISC-V Simulator for Computer Architectures Classes talk is scheduled on Thursday, November 3, 17:30 CET (16:30 UTC).

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