refactor

cvut · Jun 9, 2024 · 909e87e · 909e87e
1 parent b026b6d
commit 909e87e
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Showing 5 changed files with 257 additions and 287 deletions.
diff --git a/src/common/string_utils.h b/src/common/string_utils.h
@@ -6,11 +6,12 @@
 namespace str {
 template<typename T>
 QString asHex(T number) {
-    if (number < 0) {
-        return QString::asprintf("-0x%x", -number);
-    } else {
+    // return QString("0x%1").arg(number, 0, 16);
+    // if (number < 0) {
+    //     return QString::asprintf("-0x%x", -number);
+    // } else {
         return QString::asprintf("0x%x", number);
-    }
+    // }
 }
 } // namespace str
 

diff --git a/src/machine/bitfield.h b/src/machine/bitfield.h
@@ -26,15 +26,14 @@ struct BitField {
     [[nodiscard]] T encode(T val) const {
         return ((val & (((uint64_t)1 << count) - 1)) << offset);
     }
-    [[nodiscard]] uint64_t mask() const {
-        return (((uint64_t)1 << count) - 1) << offset;
-    }
+    [[nodiscard]] uint64_t mask() const { return (((uint64_t)1 << count) - 1) << offset; }
 };
 
 template<size_t MAX_FIELD_PARTS>
 struct SplitBitField {
     cvector<BitField, MAX_FIELD_PARTS> fields;
-    size_t shift = 0;
+    size_t str_shift = 0;
+    size_t value_shift = 0;
 
     [[nodiscard]] typename decltype(fields)::const_iterator begin() const {
         return fields.cbegin();
@@ -47,11 +46,15 @@ struct SplitBitField {
             ret |= field.decode(ins) << offset;
             offset += field.count;
         }
-        return ret << shift;
+        return ret << value_shift;
+    }
+    [[nodiscard]] uint32_t decode_str(uint32_t ins) const {
+        uint32_t res = decode(ins);
+        return res >> value_shift << str_shift;
     }
     [[nodiscard]] uint32_t encode(uint32_t imm) const {
         uint32_t ret = 0;
-        imm >>= shift;
+        imm >>= str_shift;
         for (BitField field : *this) {
             ret |= field.encode(imm);
             imm >>= field.count;

diff --git a/src/machine/instruction.cpp b/src/machine/instruction.cpp
@@ -48,10 +48,12 @@ struct ArgumentDesc {
     /** Check whether given value fits into this instruction field. */
     [[nodiscard]] constexpr bool is_value_in_field_range(RegisterValue val) const {
         if (min < 0) {
-            return val.as_i64() <= max && val.as_i64() >= min;
+            int32_t val_ = val.as_i32();
+            val_ >>= arg.str_shift;
+            return val_ <= max && val_ >= min;
         } else {
-            return val.as_u64() <= static_cast<uint64_t>(max)
-                   && val.as_u64() >= static_cast<uint64_t>(min);
+            uint64_t val_ = val.as_u64() >> arg.str_shift;
+            return val_ <= static_cast<uint64_t>(max) && val_ >= static_cast<uint64_t>(min);
         }
     }
 
@@ -70,11 +72,16 @@ static const ArgumentDesc arg_desc_list[] = {
     // Shift for bit shift instructions (5bits)
     ArgumentDesc('>', 'n', 0, 0x1f, { { { 5, 20 } }, 0 }),
     // Address offset immediate (20bits), encoded in multiples of 2 bytes
-    ArgumentDesc('a', 'a', -0x80000, 0x7ffff, { { { 10, 21 }, { 1, 20 }, { 8, 12 }, { 1, 31 } }, 1 }),
+    ArgumentDesc(
+        'a',
+        'a',
+        -0x80000,
+        0x7ffff,
+        { { { 10, 21 }, { 1, 20 }, { 8, 12 }, { 1, 31 } }, 1, 0 }),
     // U-type immediate for LUI and AUIPC (20bits)
-    ArgumentDesc('u', 'n', 0, 0xfffff000, { { { 20, 12 } }, 0 }),
+    ArgumentDesc('u', 'n', 0, 0xfffff, { { { 20, 12 } }, 0, 12 }),
     // B-type immediate for branches (12 bits)
-    ArgumentDesc('p', 'p', -0x1000, 0x0fff, { { { 4, 8 }, { 6, 25 }, { 1, 7 }, { 1, 31 } }, 1 }),
+    ArgumentDesc('p', 'p', -0x1000, 0x0fff, { { { 4, 8 }, { 6, 25 }, { 1, 7 }, { 1, 31 } }, 1, 0 }),
     // Offset immediate for load instructions (12 bits)
     ArgumentDesc('o', 'o', -0x800, 0x7ff, { { { 12, 20 } }, 0 }),
     // Offset immediate for store instructions (12 bits)
@@ -84,7 +91,7 @@ static const ArgumentDesc arg_desc_list[] = {
     ArgumentDesc('Z', 'n', 0, 0x1f, { { { 5, 15 } }, 0 }),
     // 12-bit CSR address
     // (https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/riscv-opc.c;h=7e95f645c5c5fe0a7c93c64c2f1719efaec67972;hb=HEAD#l928)
-    ArgumentDesc('E', 'E', 0, 0xfff, { { { 12, 20 } }, 0 }),
+    ArgumentDesc('E', 'E', 0, 0xfff, { { { 12, 20 } }, 0, 20 }),
 };
 
 static const ArgumentDesc *arg_desc_by_code[(int)('z' + 1)];
@@ -786,10 +793,11 @@ QString Instruction::to_str(Address inst_addr) const {
                 res += arg_letter;
                 continue;
             }
-            auto field = (int32_t)arg_desc->arg.decode(this->dt);
+
+            auto field = (int32_t)arg_desc->arg.decode_str(this->dt);
             if (arg_desc->min < 0) {
                 field = extend(field, [&]() {
-                    int sum = (int)arg_desc->arg.shift;
+                    int sum = (int)arg_desc->arg.str_shift;
                     for (auto chunk : arg_desc->arg) {
                         sum += chunk.count;
                     }
@@ -808,6 +816,7 @@ QString Instruction::to_str(Address inst_addr) const {
             case 'p':
             case 'a': {
                 field += (int32_t)inst_addr.get_raw();
+                QString a = str::asHex(field);
                 res.append(str::asHex(field));
                 break;
             }
@@ -1401,7 +1410,7 @@ bool Instruction::update(int64_t val, RelocExpression *relocexp) {
     if (relocexp->pseudo_mod != Modifier::NONE) {
         val = (int64_t)modify_pseudoinst_imm(relocexp->pseudo_mod, val);
     } else {
-        if ((val & ((1 << relocexp->arg->shift) - 1))) { return false; }
+        if ((val & ((1 << relocexp->arg->str_shift) - 1))) { return false; }
         if (relocexp->min < 0) {
             if (((int64_t)val < relocexp->min) || ((int64_t)val > relocexp->max)) {
                 if (((int64_t)val - 0x100000000 < relocexp->min)