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Render VGA from the output of a Verilog or VHDL simulation

GPL-2.0 license

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Name		Name	Last commit message	Last commit date
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evolucion		evolucion
LICENSE		LICENSE
README.md		README.md
render.tcl		render.tcl
tail.sh		tail.sh

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VGARenderer

Render VGA from the output of a Verilog or VHDL simulation

More info: https://seguridad-agile.blogspot.com/2019/12/vga-rendering-de-simulacion-fpga.html

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Render VGA from the output of a Verilog or VHDL simulation

GPL-2.0 license

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