"svtoys" is a library of diversions to demonstrate how to abuse the SystemVerilog language to play games. According to the IEEE 1800-2009 specification, SystemVerilog is a "unified hardware design, specification, and verification standard language". According to me, it is a design-by-committee, Frankenstein monster of a language. Nevertheless, it has many features that are super awesome. In particular, we enjoy using the random constraint solver to do things such as solve Sudoku puzzles.
All targets are compiled and tested using Synopsys VCS. SystemVerilog is a notoriously vendor-dependent language implementation, so we do not guarantee that this code will work on your simulator of choice.