Skip to content

Commit 6bbb5c3

Browse files
unlsycnsequencer
unlsycn
authored and
sequencer
committed
[rtl] switch to Blackbox-base SRAM
Signed-off-by: unlsycn <[email protected]>
1 parent 4838af2 commit 6bbb5c3

File tree

9 files changed

+22
-22
lines changed

9 files changed

+22
-22
lines changed

‎elaborator/src/rocketv/Frontend.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
55
import chisel3.experimental.util.SerializableModuleElaborator
66
import chisel3.util.BitPat
77
import chisel3.util.experimental.BitSet
8-
import chisel3.stage.IncludeUtilMetadata
8+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
99
import mainargs._
1010
import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter}
1111

@@ -137,7 +137,7 @@ object Frontend extends SerializableModuleElaborator {
137137
implicit def FrontendParameterMainParser: ParserForClass[FrontendParameterMain] =
138138
ParserForClass[FrontendParameterMain]
139139

140-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
140+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
141141

142142
@main
143143
def config(@arg(name = "parameter") parameter: M) =

‎elaborator/src/rocketv/ICache.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
package org.chipsalliance.t1.elaborator.rocketv
44

55
import chisel3.experimental.util.SerializableModuleElaborator
6-
import chisel3.stage.IncludeUtilMetadata
6+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
77
import mainargs._
88
import org.chipsalliance.rocketv.{ICache, ICacheParameter}
99

@@ -42,7 +42,7 @@ object ICache extends SerializableModuleElaborator {
4242

4343
implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain]
4444

45-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
45+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
4646

4747
@main
4848
def config(@arg(name = "parameter") parameter: M) =

‎elaborator/src/rocketv/RocketTile.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
55
import chisel3.experimental.util.SerializableModuleElaborator
66
import chisel3.util.BitPat
77
import chisel3.util.experimental.BitSet
8-
import chisel3.stage.IncludeUtilMetadata
8+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
99
import mainargs._
1010
import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter}
1111

@@ -191,7 +191,7 @@ object RocketTile extends SerializableModuleElaborator {
191191
implicit def RocketTileParameterMainParser: ParserForClass[RocketTileParameterMain] =
192192
ParserForClass[RocketTileParameterMain]
193193

194-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
194+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
195195

196196
@main
197197
def config(@arg(name = "parameter") parameter: M) =

‎elaborator/src/t1/T1.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
package org.chipsalliance.t1.elaborator.t1
44

55
import chisel3.experimental.util.SerializableModuleElaborator
6-
import chisel3.stage.IncludeUtilMetadata
6+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
77
import mainargs._
88
import org.chipsalliance.t1.rtl.vrf.RamType
99
import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -59,7 +59,7 @@ object T1 extends SerializableModuleElaborator {
5959

6060
implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
6161

62-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
62+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
6363

6464
@main
6565
def config(@arg(name = "parameter") parameter: M) =

‎elaborator/src/t1emu/TestBench.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
package org.chipsalliance.t1.elaborator.t1emu
44

55
import chisel3.experimental.util.SerializableModuleElaborator
6-
import chisel3.stage.IncludeUtilMetadata
6+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
77
import mainargs._
88
import org.chipsalliance.t1.rtl.vrf.RamType
99
import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -60,7 +60,7 @@ object TestBench extends SerializableModuleElaborator {
6060

6161
implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
6262

63-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
63+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
6464

6565
@main
6666
def config(@arg(name = "parameter") parameter: M) =

‎elaborator/src/t1rocket/T1RocketTile.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketv
55
import chisel3.experimental.util.SerializableModuleElaborator
66
import chisel3.util.BitPat
77
import chisel3.util.experimental.BitSet
8-
import chisel3.stage.IncludeUtilMetadata
8+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
99
import mainargs._
1010
import org.chipsalliance.t1.rtl.VFUInstantiateParameter
1111
import org.chipsalliance.t1.rtl.vrf.RamType
@@ -112,7 +112,7 @@ object T1RocketTile extends SerializableModuleElaborator {
112112
implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
113113
ParserForClass[T1RocketTileParameterMain]
114114

115-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
115+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
116116

117117
@main
118118
def config(@arg(name = "parameter") parameter: M) =

‎elaborator/src/t1rocketemu/TestBench.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketemu
55
import chisel3.experimental.util.SerializableModuleElaborator
66
import chisel3.util.BitPat
77
import chisel3.util.experimental.BitSet
8-
import chisel3.stage.IncludeUtilMetadata
8+
import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
99
import mainargs._
1010
import org.chipsalliance.t1.rtl.VFUInstantiateParameter
1111
import org.chipsalliance.t1.rtl.vrf.RamType
@@ -113,7 +113,7 @@ object TestBench extends SerializableModuleElaborator {
113113
implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
114114
ParserForClass[T1RocketTileParameterMain]
115115

116-
override def additionalAnnotations = Seq(IncludeUtilMetadata)
116+
override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
117117

118118
@main
119119
def config(@arg(name = "parameter") parameter: M) =

‎nix/t1/dependencies/_sources/generated.json

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
},
4242
"chisel": {
4343
"cargoLocks": null,
44-
"date": "2024-12-07",
44+
"date": "2024-12-08",
4545
"extract": null,
4646
"name": "chisel",
4747
"passthru": null,
@@ -53,11 +53,11 @@
5353
"name": null,
5454
"owner": "chipsalliance",
5555
"repo": "chisel",
56-
"rev": "5871a65195c7ad96edb9c58dd94cddd942815dfb",
57-
"sha256": "sha256-0xh7Xg2vi+GmoTQHNFJPQ5MP7r1UDmiGcJUI45YE16A=",
56+
"rev": "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f",
57+
"sha256": "sha256-s6y4jlTvh4q6mWXCGzxxUtFaekZ9BDT9FhrSqvtWnwE=",
5858
"type": "github"
5959
},
60-
"version": "5871a65195c7ad96edb9c58dd94cddd942815dfb"
60+
"version": "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f"
6161
},
6262
"chisel-interface": {
6363
"cargoLocks": null,

‎nix/t1/dependencies/_sources/generated.nix

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,15 +27,15 @@
2727
};
2828
chisel = {
2929
pname = "chisel";
30-
version = "5871a65195c7ad96edb9c58dd94cddd942815dfb";
30+
version = "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f";
3131
src = fetchFromGitHub {
3232
owner = "chipsalliance";
3333
repo = "chisel";
34-
rev = "5871a65195c7ad96edb9c58dd94cddd942815dfb";
34+
rev = "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f";
3535
fetchSubmodules = false;
36-
sha256 = "sha256-0xh7Xg2vi+GmoTQHNFJPQ5MP7r1UDmiGcJUI45YE16A=";
36+
sha256 = "sha256-s6y4jlTvh4q6mWXCGzxxUtFaekZ9BDT9FhrSqvtWnwE=";
3737
};
38-
date = "2024-12-07";
38+
date = "2024-12-08";
3939
};
4040
chisel-interface = {
4141
pname = "chisel-interface";

0 commit comments

Comments
 (0)