make FixedIOBaseModule work with D/I (#4216)

Author: sequencer

src/main/scala/chisel3/FixedIOModule.scala

@@ -2,17 +2,20 @@
 
 package chisel3
 
+import chisel3.experimental.hierarchy.{instantiable, public}
 import chisel3.experimental.{BaseModule, ExtModule, Param}
 
 /** A module or external module whose IO is generated from a specific generator.
   * This module may have no additional IO created other than what is specified
   * by its `ioGenerator` abstract member.
   */
+@instantiable
 sealed trait FixedIOBaseModule[A <: Data] extends BaseModule {
 
   /** A generator of IO */
   protected def ioGenerator: A
 
+  @public
   final val io = FlatIO(ioGenerator)
   endIOCreation()
 

src/test/scala/chiselTests/FixedIOModuleSpec.scala

@@ -7,6 +7,7 @@ import circt.stage.ChiselStage
 import scala.collection.immutable.ListMap
 import chisel3.reflect.DataMirror.internal.chiselTypeClone
 import chisel3.experimental.SourceInfo
+import chisel3.experimental.hierarchy.{instantiable, Definition, Instance, Instantiate}
 import chisel3.probe.Probe
 
 class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
@@ -255,4 +256,21 @@ class FixedIOModuleSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
     )()
   }
 
+  "FixedIOModule" should "work with D/I API" in {
+
+    class Foo(width: Int) extends FixedIORawModule[UInt](UInt(width.W)) {
+      io :<>= DontCare
+    }
+
+    class Bar extends RawModule {
+      val fooDef = Definition(new Foo(8))
+      val foo1 = Instance(fooDef)
+      val foo2 = Instance(fooDef)
+      foo1.io :<>= DontCare
+      foo2.io :<>= DontCare
+    }
+
+    matchesAndOmits(ChiselStage.emitCHIRRTL(new Bar))("module Foo :")()
+  }
+
 }