Low dropout Voltage Regulator(LDO) using SKY130PDK

Design of Low dropout voltage regulator with a voltage drop of 150mV for a regulated output of 1.35V for an input range of 1.5-3V using SKY130PDK

Specification

Circuit

Schematics

Line, Load regulation and PSRR

• Achieved specififcations:
  
  • DC gain: 50 dB
    
  • GBW: 4.8 MHz
    
  • Phase Margin: 86°
    
  • PSRR : 50dB
    
  • Efficiency: 89.77%
    
  • IQ: 105μA(I've burnt more current to to get the desired tset)
    
  • tset (Load): 1μsec
  • tset (Line): 2μsec
  • Maximum Vreg variation with temperature(-45°C to 125°C): 1.358V-1.349V
    
    

Load Regulation

Line Regulation

Load + Line Regulation

Quiscent Current

Load Transient

Line Transient

Temperature Variation

Phase Margin

PSRR

References

[1]. A Low Drop Regulator (LDO) in UMC 180 nm Technology by Mohammed Rizwan
[2]. Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison by Joselyn Torres, Mohamed ElNozahi, Ahmed Amer, Seenu Gopalraju, Reza Abdullah, Kamran Entesari, and Edgar S·nchez-Sinencio.
[3]. Full On-Chip CMOS Low-Dropout Voltage Regulator Robert J. Milliken, Jose Silva-MartÌnez.
[4]. IC Design of Power Management Circuits (IV) Wing-Hung Ki Integrated Power Electronics Laboratory ECE Dept., HKUST Clear Water Bay, Hong Kong.
[5]. Design of low-dropout voltage regulator Miroslav Čermák.
[6]. LDO Linear Regulator to Charge Battery by Ahmed tawfiq.
[7]. Power Management Integrated Circuits NPTEL-NOC IITM by Qadeer Ahmed Khan (https://youtube.com/playlist?list=PLyqSpQzTE6M9UpgVUKY3QKnVVlcqFrMM1&si=mBEvuR-5jQblesC)
[8]. Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate by Marouf Khan and Masud H. Chowdhury.
[9]. Y. Wang, X. Wang and H. Yao, "Design of a foldback current limit circuit in LDO.
[10]. A_Novel_Fold-Back_Current_Limiting_Protection_used_in_Sub threshold LDO for Wireless Sensor Applications, Chen, Ziyue.