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scaprilescaprile
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Add support for GbE
1 parent c129897 commit 69925c7

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2 files changed

+30
-21
lines changed

2 files changed

+30
-21
lines changed

‎mongoose.c‎

Lines changed: 19 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -23446,8 +23446,8 @@ enum { // ID1 ID2
2344623446
MG_PHY_DP83848 = 0x5ca2, // 2000 5ca2 - TI DP83848I
2344723447
MG_PHY_LAN87x = 0x7, // 0007 c0fx - LAN8720
2344823448
MG_PHY_RTL82x = 0x1c,
23449-
MG_PHY_RTL8201 = 0xc816, // 001c c816 - RTL8201,
23450-
MG_PHY_RTL8211 = 0xc916, // 001c c916 - RTL8201,
23449+
MG_PHY_RTL8201 = 0xc816, // 001c c816 - RTL8201F
23450+
MG_PHY_RTL8211 = 0xc916, // 001c c916 - RTL8211F
2345123451
MG_PHY_ICS1894x = 0x15,
2345223452
MG_PHY_ICS189432 = 0xf450 // 0015 f450 - ICS1894
2345323453
};
@@ -23464,10 +23464,9 @@ enum {
2346423464
MG_PHY_KSZ8x_REG_PC1R = 30,
2346523465
MG_PHY_KSZ8x_REG_PC2R = 31,
2346623466
MG_PHY_LAN87x_REG_SCSR = 31,
23467-
MG_PHY_RTL8201_REG_RMSR = 16, // in page 7
23468-
MG_PHY_RTL8201_REG_PAGESEL = 31,
23467+
MG_PHY_RTL82x_REG_PAGESEL = 31,
23468+
MG_PHY_RTL8201_REG_RMSR = 16, // in page 7
2346923469
MG_PHY_RTL8211_REG_PHYSR = 26, // in page a43
23470-
MG_PHY_RTL8211_REG_PAGESEL = 31,
2347123470
MG_PHY_ICS189432_REG_POLL = 17
2347223471
};
2347323472

@@ -23542,9 +23541,9 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
2354223541
} else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8201) {
2354323542
// assume PHY has been hardware strapped properly
2354423543
#if 0
23545-
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 7); // Select page 7
23544+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 7); // Select page 7
2354623545
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_RMSR, 0x1ffa);
23547-
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 0); // Select page 0
23546+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 0); // Select page 0
2354823547
#endif
2354923548
} else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8211) {
2355023549
// assume PHY has been hardware strapped properly
@@ -23591,9 +23590,9 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
2359123590
uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
2359223591
if (id2 == MG_PHY_RTL8211) {
2359323592
uint16_t physr;
23594-
phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0xa43);
23593+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 0xa43);
2359523594
physr = phy->read_reg(phy_addr, MG_PHY_RTL8211_REG_PHYSR);
23596-
phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0);
23595+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 0);
2359723596
*full_duplex = physr & MG_BIT(3);
2359823597
*speed = (physr & MG_BIT(5)) ? MG_PHY_SPEED_1000M
2359923598
: (physr & MG_BIT(4)) ? MG_PHY_SPEED_100M
@@ -25336,11 +25335,13 @@ struct synopsys_enet_qos {
2533625335
#define ETH_DESC_CNT 4 // Descriptors count
2533725336
#define ETH_DS 4 // Descriptor size (words)
2533825337

25339-
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
25340-
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
25338+
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM
25339+
MG_8BYTE_ALIGNED;
25340+
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM
25341+
MG_8BYTE_ALIGNED;
2534125342
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
2534225343
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
25343-
static struct mg_tcpip_if *s_ifp; // MIP interface
25344+
static struct mg_tcpip_if *s_ifp; // MIP interface
2534425345

2534525346
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
2534625347
ETH->MACMDIOAR &= (0xF << 8);
@@ -25416,7 +25417,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
2541625417
#endif
2541725418
ETH->DMACIER = MG_BIT(6) | MG_BIT(15); // RIE, NIE
2541825419
ETH->MACCR = MG_BIT(0) | MG_BIT(1) | MG_BIT(13) | MG_BIT(14) |
25419-
MG_BIT(15); // RE, TE, Duplex, Fast, Reserved
25420+
MG_BIT(15); // RE, TE, Duplex, Fast, (10/100)/Reserved
2542025421
#if MG_ENABLE_DRIVER_STM32H
2542125422
ETH->MTLTQOMR |= MG_BIT(1); // TSF
2542225423
ETH->MTLRQOMR |= MG_BIT(5); // RSF
@@ -25494,8 +25495,11 @@ static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
2549425495
// if(link is slow or half) set flags otherwise
2549525496
// reg = tmp
2549625497
uint32_t maccr = ETH->MACCR | MG_BIT(14) | MG_BIT(13); // 100M, Full-duplex
25497-
if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
25498-
if (full_duplex == false) maccr &= ~MG_BIT(13); // Half-duplex
25498+
#if MG_ENABLE_DRIVER_STM32N
25499+
if (speed == MG_PHY_SPEED_1000M) maccr &= ~MG_BIT(15); // 1000M
25500+
#endif
25501+
if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
25502+
if (full_duplex == false) maccr &= ~MG_BIT(13); // Half-duplex
2549925503
ETH->MACCR = maccr; // IRQ handler does not fiddle with this register
2550025504
MG_DEBUG(("Link is %uM %s-duplex", maccr & MG_BIT(14) ? 100 : 10,
2550125505
maccr & MG_BIT(13) ? "full" : "half"));

‎src/drivers/stm32h.c‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,11 +50,13 @@ struct synopsys_enet_qos {
5050
#define ETH_DESC_CNT 4 // Descriptors count
5151
#define ETH_DS 4 // Descriptor size (words)
5252

53-
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
54-
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM MG_8BYTE_ALIGNED;
53+
static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM
54+
MG_8BYTE_ALIGNED;
55+
static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS] MG_ETH_RAM
56+
MG_8BYTE_ALIGNED;
5557
static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
5658
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_ETH_RAM MG_8BYTE_ALIGNED;
57-
static struct mg_tcpip_if *s_ifp; // MIP interface
59+
static struct mg_tcpip_if *s_ifp; // MIP interface
5860

5961
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
6062
ETH->MACMDIOAR &= (0xF << 8);
@@ -130,7 +132,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
130132
#endif
131133
ETH->DMACIER = MG_BIT(6) | MG_BIT(15); // RIE, NIE
132134
ETH->MACCR = MG_BIT(0) | MG_BIT(1) | MG_BIT(13) | MG_BIT(14) |
133-
MG_BIT(15); // RE, TE, Duplex, Fast, Reserved
135+
MG_BIT(15); // RE, TE, Duplex, Fast, (10/100)/Reserved
134136
#if MG_ENABLE_DRIVER_STM32H
135137
ETH->MTLTQOMR |= MG_BIT(1); // TSF
136138
ETH->MTLRQOMR |= MG_BIT(5); // RSF
@@ -208,8 +210,11 @@ static bool mg_tcpip_driver_stm32h_poll(struct mg_tcpip_if *ifp, bool s1) {
208210
// if(link is slow or half) set flags otherwise
209211
// reg = tmp
210212
uint32_t maccr = ETH->MACCR | MG_BIT(14) | MG_BIT(13); // 100M, Full-duplex
211-
if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
212-
if (full_duplex == false) maccr &= ~MG_BIT(13); // Half-duplex
213+
#if MG_ENABLE_DRIVER_STM32N
214+
if (speed == MG_PHY_SPEED_1000M) maccr &= ~MG_BIT(15); // 1000M
215+
#endif
216+
if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
217+
if (full_duplex == false) maccr &= ~MG_BIT(13); // Half-duplex
213218
ETH->MACCR = maccr; // IRQ handler does not fiddle with this register
214219
MG_DEBUG(("Link is %uM %s-duplex", maccr & MG_BIT(14) ? 100 : 10,
215220
maccr & MG_BIT(13) ? "full" : "half"));

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