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scaprilescaprile
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Merge pull request #3367 from cesanta/rtl8211
Add support for RTL8211
2 parents 767b0ab + bedda34 commit c129897

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2 files changed

+69
-20
lines changed

2 files changed

+69
-20
lines changed

‎mongoose.c‎

Lines changed: 33 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -23445,7 +23445,9 @@ enum { // ID1 ID2
2344523445
MG_PHY_DP83825 = 0xa140, // 2000 a140 - TI DP83825I
2344623446
MG_PHY_DP83848 = 0x5ca2, // 2000 5ca2 - TI DP83848I
2344723447
MG_PHY_LAN87x = 0x7, // 0007 c0fx - LAN8720
23448-
MG_PHY_RTL8201 = 0x1C, // 001c c816 - RTL8201,
23448+
MG_PHY_RTL82x = 0x1c,
23449+
MG_PHY_RTL8201 = 0xc816, // 001c c816 - RTL8201,
23450+
MG_PHY_RTL8211 = 0xc916, // 001c c916 - RTL8201,
2344923451
MG_PHY_ICS1894x = 0x15,
2345023452
MG_PHY_ICS189432 = 0xf450 // 0015 f450 - ICS1894
2345123453
};
@@ -23464,6 +23466,8 @@ enum {
2346423466
MG_PHY_LAN87x_REG_SCSR = 31,
2346523467
MG_PHY_RTL8201_REG_RMSR = 16, // in page 7
2346623468
MG_PHY_RTL8201_REG_PAGESEL = 31,
23469+
MG_PHY_RTL8211_REG_PHYSR = 26, // in page a43
23470+
MG_PHY_RTL8211_REG_PAGESEL = 31,
2346723471
MG_PHY_ICS189432_REG_POLL = 17
2346823472
};
2346923473

@@ -23484,8 +23488,15 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
2348423488
return "KSZ8x";
2348523489
case MG_PHY_LAN87x:
2348623490
return "LAN87x";
23487-
case MG_PHY_RTL8201:
23488-
return "RTL8201";
23491+
case MG_PHY_RTL82x:
23492+
switch (id2) {
23493+
case MG_PHY_RTL8201:
23494+
return "RTL8201";
23495+
case MG_PHY_RTL8211:
23496+
return "RTL8211";
23497+
default:
23498+
return "RTL82x";
23499+
}
2348923500
case MG_PHY_ICS1894x:
2349023501
return "ICS1894x";
2349123502
default:
@@ -23528,13 +23539,15 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
2352823539
(uint16_t) (MG_BIT(15) | MG_BIT(8) | MG_BIT(7)));
2352923540
} else if (id1 == MG_PHY_LAN87x) {
2353023541
// nothing to do
23531-
} else if (id1 == MG_PHY_RTL8201) {
23542+
} else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8201) {
2353223543
// assume PHY has been hardware strapped properly
2353323544
#if 0
2353423545
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 7); // Select page 7
2353523546
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_RMSR, 0x1ffa);
2353623547
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 0); // Select page 0
2353723548
#endif
23549+
} else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8211) {
23550+
// assume PHY has been hardware strapped properly
2353823551
}
2353923552
}
2354023553

@@ -23574,10 +23587,22 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
2357423587
uint16_t scsr = phy->read_reg(phy_addr, MG_PHY_LAN87x_REG_SCSR);
2357523588
*full_duplex = scsr & MG_BIT(4);
2357623589
*speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
23577-
} else if (id1 == MG_PHY_RTL8201) {
23578-
uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
23579-
*full_duplex = bcr & MG_BIT(8);
23580-
*speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
23590+
} else if (id1 == MG_PHY_RTL82x) {
23591+
uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
23592+
if (id2 == MG_PHY_RTL8211) {
23593+
uint16_t physr;
23594+
phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0xa43);
23595+
physr = phy->read_reg(phy_addr, MG_PHY_RTL8211_REG_PHYSR);
23596+
phy->write_reg(phy_addr, MG_PHY_RTL8211_REG_PAGESEL, 0);
23597+
*full_duplex = physr & MG_BIT(3);
23598+
*speed = (physr & MG_BIT(5)) ? MG_PHY_SPEED_1000M
23599+
: (physr & MG_BIT(4)) ? MG_PHY_SPEED_100M
23600+
: MG_PHY_SPEED_10M;
23601+
} else {
23602+
uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
23603+
*full_duplex = bcr & MG_BIT(8);
23604+
*speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
23605+
}
2358123606
} else if (id1 == MG_PHY_ICS1894x) {
2358223607
uint16_t poll_reg = phy->read_reg(phy_addr, MG_PHY_ICS189432_REG_POLL);
2358323608
*full_duplex = poll_reg & MG_BIT(14);

‎src/drivers/phy.c‎

Lines changed: 36 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,9 @@ enum { // ID1 ID2
77
MG_PHY_DP83825 = 0xa140, // 2000 a140 - TI DP83825I
88
MG_PHY_DP83848 = 0x5ca2, // 2000 5ca2 - TI DP83848I
99
MG_PHY_LAN87x = 0x7, // 0007 c0fx - LAN8720
10-
MG_PHY_RTL8201 = 0x1C, // 001c c816 - RTL8201,
10+
MG_PHY_RTL82x = 0x1c,
11+
MG_PHY_RTL8201 = 0xc816, // 001c c816 - RTL8201F
12+
MG_PHY_RTL8211 = 0xc916, // 001c c916 - RTL8211F
1113
MG_PHY_ICS1894x = 0x15,
1214
MG_PHY_ICS189432 = 0xf450 // 0015 f450 - ICS1894
1315
};
@@ -24,8 +26,9 @@ enum {
2426
MG_PHY_KSZ8x_REG_PC1R = 30,
2527
MG_PHY_KSZ8x_REG_PC2R = 31,
2628
MG_PHY_LAN87x_REG_SCSR = 31,
27-
MG_PHY_RTL8201_REG_RMSR = 16, // in page 7
28-
MG_PHY_RTL8201_REG_PAGESEL = 31,
29+
MG_PHY_RTL82x_REG_PAGESEL = 31,
30+
MG_PHY_RTL8201_REG_RMSR = 16, // in page 7
31+
MG_PHY_RTL8211_REG_PHYSR = 26, // in page a43
2932
MG_PHY_ICS189432_REG_POLL = 17
3033
};
3134

@@ -46,8 +49,15 @@ static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
4649
return "KSZ8x";
4750
case MG_PHY_LAN87x:
4851
return "LAN87x";
49-
case MG_PHY_RTL8201:
50-
return "RTL8201";
52+
case MG_PHY_RTL82x:
53+
switch (id2) {
54+
case MG_PHY_RTL8201:
55+
return "RTL8201";
56+
case MG_PHY_RTL8211:
57+
return "RTL8211";
58+
default:
59+
return "RTL82x";
60+
}
5161
case MG_PHY_ICS1894x:
5262
return "ICS1894x";
5363
default:
@@ -90,13 +100,15 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
90100
(uint16_t) (MG_BIT(15) | MG_BIT(8) | MG_BIT(7)));
91101
} else if (id1 == MG_PHY_LAN87x) {
92102
// nothing to do
93-
} else if (id1 == MG_PHY_RTL8201) {
103+
} else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8201) {
94104
// assume PHY has been hardware strapped properly
95105
#if 0
96-
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 7); // Select page 7
106+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 7); // Select page 7
97107
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_RMSR, 0x1ffa);
98-
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 0); // Select page 0
108+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 0); // Select page 0
99109
#endif
110+
} else if (id1 == MG_PHY_RTL82x && id2 == MG_PHY_RTL8211) {
111+
// assume PHY has been hardware strapped properly
100112
}
101113
}
102114

@@ -136,10 +148,22 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
136148
uint16_t scsr = phy->read_reg(phy_addr, MG_PHY_LAN87x_REG_SCSR);
137149
*full_duplex = scsr & MG_BIT(4);
138150
*speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
139-
} else if (id1 == MG_PHY_RTL8201) {
140-
uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
141-
*full_duplex = bcr & MG_BIT(8);
142-
*speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
151+
} else if (id1 == MG_PHY_RTL82x) {
152+
uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
153+
if (id2 == MG_PHY_RTL8211) {
154+
uint16_t physr;
155+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 0xa43);
156+
physr = phy->read_reg(phy_addr, MG_PHY_RTL8211_REG_PHYSR);
157+
phy->write_reg(phy_addr, MG_PHY_RTL82x_REG_PAGESEL, 0);
158+
*full_duplex = physr & MG_BIT(3);
159+
*speed = (physr & MG_BIT(5)) ? MG_PHY_SPEED_1000M
160+
: (physr & MG_BIT(4)) ? MG_PHY_SPEED_100M
161+
: MG_PHY_SPEED_10M;
162+
} else {
163+
uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
164+
*full_duplex = bcr & MG_BIT(8);
165+
*speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
166+
}
143167
} else if (id1 == MG_PHY_ICS1894x) {
144168
uint16_t poll_reg = phy->read_reg(phy_addr, MG_PHY_ICS189432_REG_POLL);
145169
*full_duplex = poll_reg & MG_BIT(14);

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