re-added pmod sync-inout in firmware

modem spi freq 4MHz
cariboulabs · Apr 9, 2024 · 211e5a3 · 211e5a3
1 parent ffbd7af
commit 211e5a3
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Showing 20 changed files with 25,807 additions and 25,414 deletions.
diff --git a/driver/smi_stream_dev.c b/driver/smi_stream_dev.c
@@ -254,15 +254,30 @@ static int set_state(smi_stream_state_en new_state)
         return 0;
     }
 
-
     // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer
     if(new_state != smi_stream_idle)
     {
         bcm2835_smi_set_address(inst->smi_inst, new_address);
 
         if (new_state == smi_stream_tx_channel)
         {
-            ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
+            // remove all data inside the tx_fifo
+            if (mutex_lock_interruptible(&inst->write_lock))
+            {
+                return -EINTR;
+            }
+            kfifo_reset(&inst->tx_fifo);
+            mutex_unlock(&inst->write_lock);
+
+            inst->writeable = true;
+            wake_up_interruptible(&inst->poll_event);
+
+            //ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
+            mb();
+            spin_unlock(&inst->state_lock);
+
+            // return the success
+            return ret;
         }
         else
         {
@@ -734,7 +749,7 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe
         struct dma_async_tx_descriptor *desc = NULL;
         struct bcm2835_smi_instance *smi_inst = inst->smi_inst;
         spin_lock(&smi_inst->transaction_lock);
-        desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback,inst);
+        desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback, inst);
 
         if(desc)
         {
@@ -886,15 +901,6 @@ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr
         return -EAGAIN;
     }
 
-    if (kfifo_is_full(&inst->tx_fifo))
-    {
-        if(wait_event_interruptible(inst->poll_event,  !kfifo_is_full(&inst->tx_fifo)))
-        {
-            mutex_unlock(&inst->write_lock);
-            return -EAGAIN;
-        }	
-    }
-
     // check how many bytes are available in the tx fifo
     num_bytes_available = kfifo_avail(&inst->tx_fifo);
     num_to_push = num_bytes_available > count ? count : num_bytes_available;

diff --git a/examples/cpp_api/async_sample_process/main.cpp b/examples/cpp_api/async_sample_process/main.cpp
@@ -152,12 +152,12 @@ void dataConsumerThread(appContext_st* app)
 // Rx Callback (async)
 void receivedSamples(CaribouLiteRadio* radio, const std::complex<float>* samples, CaribouLiteMeta* sync, size_t num_samples)
 {
-    for (int i = 0; i < 6; i ++)
+    /*for (int i = 0; i < 6; i ++)
     {
         std::cout << "[" << samples[i].real() << ", " << samples[i].imag() << "]";
     }
     std::cout << std::endl;
-
+    */
     // push the received samples in the fifo
     app.rx_fifo->put(samples, num_samples);
 }

diff --git a/firmware/.gitignore.bak b/firmware/.gitignore.bak
@@ -1,56 +0,0 @@
-# Prerequisites
-*.d
-
-# Object files
-*.o
-*.ko
-*.obj
-*.elf
-
-# Linker output
-*.ilk
-*.map
-*.exp
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-*.su
-*.idb
-*.pdb
-
-# Kernel Module Compile Results
-*.mod*
-*.cmd
-.tmp_versions/
-modules.order
-Module.symvers
-Mkfile.old
-dkms.conf
-
-# build directories
-installations
-build

diff --git a/firmware/Makefile b/firmware/Makefile
@@ -4,9 +4,9 @@ pcf_file = ./io.pcf
 
 top.bin:
 	yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v
+
 	#nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc
-	nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 5 --timing-allow-fail
-	#nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui
+	nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --parallel-refine --opt-timing --seed 16 --timing-allow-fail
 	icepack $(filename).asc $(filename).bin
 
 build: top.bin

diff --git a/firmware/complex_fifo.v b/firmware/complex_fifo.v
@@ -15,9 +15,6 @@ module complex_fifo #(
 
 	output reg 						full_o,
 	output reg 						empty_o,
-
-	input wire						debug_pull,
-	input wire						debug_push,
 );
 
 	reg [ADDR_WIDTH-1:0]	wr_addr;
@@ -29,7 +26,15 @@ module complex_fifo #(
 	reg [ADDR_WIDTH-1:0]	rd_addr_gray_wr;
 	reg [ADDR_WIDTH-1:0]	rd_addr_gray_wr_r;
 
-	reg [2*DATA_WIDTH-1:0] 	debug_buffer;
+	// Initial conditions
+	initial begin
+		wr_addr <= 0;
+		wr_addr_gray <= 0;
+		full_o <= 0;
+		rd_addr <= 0;
+		rd_addr_gray <= 0;
+		empty_o <= 1'b1;
+	end
 
 	function [ADDR_WIDTH-1:0] gray_conv;
 		input [ADDR_WIDTH-1:0] in;
@@ -38,7 +43,7 @@ module complex_fifo #(
 		end
 	endfunction
 
-	always @(posedge wr_clk_i) begin
+	always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
 		if (wr_rst_b_i == 1'b0) begin
 			wr_addr <= 0;
 			wr_addr_gray <= 0;
@@ -54,7 +59,7 @@ module complex_fifo #(
 		rd_addr_gray_wr_r <= rd_addr_gray_wr;
 	end
 
-	always @(posedge wr_clk_i) begin
+	always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
 		if (wr_rst_b_i == 1'b0) begin
 			full_o <= 0;
 		end else if (wr_en_i) begin
@@ -64,11 +69,10 @@ module complex_fifo #(
 		end
 	end
 
-	always @(posedge rd_clk_i) begin
+	always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
 		if (rd_rst_b_i == 1'b0) begin
 			rd_addr <= 0;
 			rd_addr_gray <= 0;
-			debug_buffer <= 32'hABCDEF01;
 		end else if (rd_en_i) begin
 			rd_addr <= rd_addr + 1'b1;
 			rd_addr_gray <= gray_conv(rd_addr + 1'b1);
@@ -81,7 +85,7 @@ module complex_fifo #(
 		wr_addr_gray_rd_r <= wr_addr_gray_rd;
 	end
 
-	always @(posedge rd_clk_i) begin
+	always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
 		if (rd_rst_b_i == 1'b0) begin
 			empty_o <= 1'b1;
 		end else if (rd_en_i) begin
@@ -93,24 +97,15 @@ module complex_fifo #(
 
 	always @(posedge rd_clk_i) begin
 		if (rd_en_i) begin
-			if (debug_pull) begin
-				rd_data_o <= debug_buffer;
-			end else begin
-				rd_data_o[15:0] <= mem_q[rd_addr][15:0];
-				rd_data_o[31:16] <= mem_i[rd_addr][15:0];
-			end
+			rd_data_o[15:0] <= mem_q[rd_addr][15:0];
+			rd_data_o[31:16] <= mem_i[rd_addr][15:0];
 		end
 	end
 
 	always @(posedge wr_clk_i) begin
 		if (wr_en_i) begin
-			if (debug_push) begin
-				mem_q[wr_addr] <= debug_buffer[15:0];
-				mem_i[wr_addr] <= debug_buffer[31:16];
-			end else begin
-				mem_q[wr_addr] <= wr_data_i[15:0];
-				mem_i[wr_addr] <= wr_data_i[31:16];
-			end
+			mem_q[wr_addr] <= wr_data_i[15:0];
+			mem_i[wr_addr] <= wr_data_i[31:16];
 		end
 	end