Fix clippy warnings

capstone-rs/src/arch/arm.rs

@@ -171,7 +171,7 @@ pub enum ArmOperandType {
 #[derive(Debug, Copy, Clone)]
 pub struct ArmOpMem(pub(crate) arm_op_mem);
 
-impl<'a> ArmInsnDetail<'a> {
+impl ArmInsnDetail<'_> {
     /// Whether the instruction is a user mode
     pub fn usermode(&self) -> bool {
         self.0.usermode
@@ -263,7 +263,7 @@ impl Default for ArmOperand {
     }
 }
 
-impl<'a> From<&'a cs_arm_op> for ArmOperand {
+impl From<&cs_arm_op> for ArmOperand {
     fn from(op: &cs_arm_op) -> ArmOperand {
         let shift = ArmShift::new(op.shift.type_, op.shift.value);
         let op_type = ArmOperandType::new(op.type_, op.__bindgen_anon_1);

capstone-rs/src/arch/arm64.rs

@@ -139,7 +139,7 @@ pub enum Arm64OperandType {
 #[derive(Debug, Copy, Clone)]
 pub struct Arm64OpMem(pub(crate) arm64_op_mem);
 
-impl<'a> Arm64InsnDetail<'a> {
+impl Arm64InsnDetail<'_> {
     /// Condition codes
     pub fn cc(&self) -> Arm64CC {
         self.0.cc
@@ -224,7 +224,7 @@ impl Arm64Shift {
     }
 }
 
-impl<'a> From<&'a cs_arm64_op> for Arm64Operand {
+impl From<&cs_arm64_op> for Arm64Operand {
     fn from(op: &cs_arm64_op) -> Arm64Operand {
         let shift = Arm64Shift::new(op.shift.type_, op.shift.value);
         let op_type = Arm64OperandType::new(op.type_, op.__bindgen_anon_1);

capstone-rs/src/arch/bpf.rs

@@ -76,7 +76,7 @@ impl_PartialEq_repr_fields!(BpfOpMem;
 
 impl cmp::Eq for BpfOpMem {}
 
-impl<'a> From<&'a cs_bpf_op> for BpfOperand {
+impl From<&cs_bpf_op> for BpfOperand {
     fn from(insn: &cs_bpf_op) -> BpfOperand {
         match insn.type_ {
             bpf_op_type::BPF_OP_EXT => BpfOperand::Ext(unsafe { insn.__bindgen_anon_1.ext }),

capstone-rs/src/arch/evm.rs

@@ -14,7 +14,7 @@ use crate::arch::DetailsArchInsn;
 /// Contains EVM-specific details for an instruction
 pub struct EvmInsnDetail<'a>(pub(crate) &'a cs_evm);
 
-impl<'a> EvmInsnDetail<'a> {
+impl EvmInsnDetail<'_> {
     /// Number of items popped from the stack
     pub fn popped_items(&self) -> u8 {
         self.0.pop
@@ -77,15 +77,15 @@ impl fmt::Debug for EvmOperandIterator {
     }
 }
 
-impl<'a> fmt::Debug for EvmInsnDetail<'a> {
+impl fmt::Debug for EvmInsnDetail<'_> {
     fn fmt(&self, fmt: &mut fmt::Formatter) -> ::core::fmt::Result {
         fmt.debug_struct("EvmInsnDetail")
             .field("cs_evm", &(self.0 as *const cs_evm))
             .finish()
     }
 }
 
-impl<'a> DetailsArchInsn for EvmInsnDetail<'a> {
+impl DetailsArchInsn for EvmInsnDetail<'_> {
     type OperandIterator = EvmOperandIterator;
     type Operand = EvmOperand;
 

capstone-rs/src/arch/m680x.rs

@@ -181,7 +181,7 @@ impl Default for M680xOperandType {
     }
 }
 
-impl<'a> From<&'a cs_m680x_op> for M680xOperand {
+impl From<&cs_m680x_op> for M680xOperand {
     fn from(op: &cs_m680x_op) -> M680xOperand {
         let op_type = match op.type_ {
             m680x_op_type::M680X_OP_REGISTER => {

capstone-rs/src/arch/m68k.rs

@@ -23,7 +23,7 @@ use crate::prelude::*;
 /// Contains M68K-specific details for an instruction
 pub struct M68kInsnDetail<'a>(pub(crate) &'a cs_m68k);
 
-impl<'a> M68kInsnDetail<'a> {
+impl M68kInsnDetail<'_> {
     /// size of data operand works on in bytes (.b, .w, .l, etc)
     pub fn op_size(&self) -> Option<M68kOpSize> {
         M68kOpSize::new(&self.0.op_size)
@@ -444,7 +444,7 @@ impl_PartialEq_repr_fields!(M68kOpMem;
 
 impl cmp::Eq for M68kOpMem {}
 
-impl<'a> From<&'a cs_m68k_op> for M68kOperand {
+impl From<&cs_m68k_op> for M68kOperand {
     fn from(insn: &cs_m68k_op) -> M68kOperand {
         M68kOperand::new(insn)
     }

capstone-rs/src/arch/mips.rs

@@ -65,7 +65,7 @@ impl_PartialEq_repr_fields!(MipsOpMem;
 
 impl cmp::Eq for MipsOpMem {}
 
-impl<'a> From<&'a cs_mips_op> for MipsOperand {
+impl From<&cs_mips_op> for MipsOperand {
     fn from(insn: &cs_mips_op) -> MipsOperand {
         match insn.type_ {
             mips_op_type::MIPS_OP_REG => {

capstone-rs/src/arch/mod.rs

@@ -610,7 +610,7 @@ macro_rules! detail_defs {
 
             $(
                 $( #[$func_attr] )+
-                pub fn $arch_name(&'a self) -> Option<& $InsnDetail> {
+                pub fn $arch_name(&'a self) -> Option<&'a $InsnDetail> {
                     if let ArchDetail::$Detail(ref arch_detail) = *self {
                         Some(arch_detail)
                     } else {

capstone-rs/src/arch/ppc.rs

@@ -18,7 +18,7 @@ use crate::instruction::{RegId, RegIdInt};
 /// Contains PPC-specific details for an instruction
 pub struct PpcInsnDetail<'a>(pub(crate) &'a cs_ppc);
 
-impl<'a> PpcInsnDetail<'a> {
+impl PpcInsnDetail<'_> {
     /// Branch code for branch instructions
     pub fn bc(&self) -> PpcBc {
         self.0.bc
@@ -115,7 +115,7 @@ impl cmp::PartialEq for PpcOpCrx {
 
 impl cmp::Eq for PpcOpCrx {}
 
-impl<'a> From<&'a cs_ppc_op> for PpcOperand {
+impl From<&cs_ppc_op> for PpcOperand {
     fn from(insn: &cs_ppc_op) -> PpcOperand {
         match insn.type_ {
             ppc_op_type::PPC_OP_REG => {

capstone-rs/src/arch/riscv.rs

@@ -64,7 +64,7 @@ impl_PartialEq_repr_fields!(RiscVOpMem;
 
 impl cmp::Eq for RiscVOpMem {}
 
-impl<'a> From<&'a cs_riscv_op> for RiscVOperand {
+impl From<&cs_riscv_op> for RiscVOperand {
     fn from(insn: &cs_riscv_op) -> RiscVOperand {
         match insn.type_ {
             riscv_op_type::RISCV_OP_REG => {

capstone-rs/src/arch/sparc.rs

@@ -35,7 +35,7 @@ pub enum SparcOperand {
     Invalid,
 }
 
-impl<'a> SparcInsnDetail<'a> {
+impl SparcInsnDetail<'_> {
     /// Condition codes
     pub fn cc(&self) -> SparcCC {
         self.0.cc
@@ -84,7 +84,7 @@ impl_PartialEq_repr_fields!(SparcOpMem;
 
 impl cmp::Eq for SparcOpMem {}
 
-impl<'a> From<&'a cs_sparc_op> for SparcOperand {
+impl From<&cs_sparc_op> for SparcOperand {
     fn from(insn: &cs_sparc_op) -> SparcOperand {
         match insn.type_ {
             sparc_op_type::SPARC_OP_REG => {

capstone-rs/src/arch/sysz.rs

@@ -77,7 +77,7 @@ impl_PartialEq_repr_fields!(SysZOpMem;
 
 impl cmp::Eq for SysZOpMem {}
 
-impl <'a> From<&'a cs_sysz_op> for SysZOperand {
+impl  From<&cs_sysz_op> for SysZOperand {
     fn from(insn: &cs_sysz_op) -> SysZOperand {
         match insn.type_ {
             sysz_op_type::SYSZ_OP_REG => {

capstone-rs/src/arch/tms320c64x.rs

@@ -40,7 +40,7 @@ define_cs_enum_wrapper_reverse!(
     => No = TMS320C64X_FUNIT_NO;
 );
 
-impl<'a> Tms320c64xInsnDetail<'a> {
+impl Tms320c64xInsnDetail<'_> {
     /// Whether condition is zero
     pub fn is_condition_zero(&self) -> bool {
         self.0.condition.zero != 0
@@ -220,7 +220,7 @@ impl_PartialEq_repr_fields!(Tms320c64xOpMem;
 
 impl cmp::Eq for Tms320c64xOpMem {}
 
-impl<'a> From<&'a cs_tms320c64x_op> for Tms320c64xOperand {
+impl From<&cs_tms320c64x_op> for Tms320c64xOperand {
     fn from(insn: &cs_tms320c64x_op) -> Tms320c64xOperand {
         match insn.type_ {
             tms320c64x_op_type::TMS320C64X_OP_REG => {

capstone-rs/src/arch/x86.rs

@@ -82,7 +82,7 @@ pub enum X86OperandType {
 #[derive(Debug, Copy, Clone)]
 pub struct X86OpMem(pub(crate) x86_op_mem);
 
-impl<'a> X86InsnDetail<'a> {
+impl X86InsnDetail<'_> {
     /// Instruction prefix, which can be up to 4 bytes.
     /// A prefix byte gets value 0 when irrelevant.
     /// See `X86Prefix` for details.
@@ -222,7 +222,7 @@ impl Default for X86Operand {
     }
 }
 
-impl<'a> From<&'a cs_x86_op> for X86Operand {
+impl From<&cs_x86_op> for X86Operand {
     fn from(op: &cs_x86_op) -> X86Operand {
         let op_type = X86OperandType::new(op.type_, op.__bindgen_anon_1);
         X86Operand {

capstone-rs/src/arch/xcore.rs

@@ -74,7 +74,7 @@ impl_PartialEq_repr_fields!(XcoreOpMem;
 
 impl cmp::Eq for XcoreOpMem {}
 
-impl<'a> From<&'a cs_xcore_op> for XcoreOperand {
+impl From<&cs_xcore_op> for XcoreOperand {
     fn from(insn: &cs_xcore_op) -> XcoreOperand {
         match insn.type_ {
             xcore_op_type::XCORE_OP_REG => {

capstone-rs/src/instruction.rs

@@ -143,7 +143,7 @@ impl<'a> AsRef<[Insn<'a>]> for Instructions<'a> {
     }
 }
 
-impl<'a> Drop for Instructions<'a> {
+impl Drop for Instructions<'_> {
     fn drop(&mut self) {
         if !self.is_empty() {
             unsafe {
@@ -199,7 +199,7 @@ pub struct Insn<'a> {
 pub struct InsnDetail<'a>(pub(crate) &'a cs_detail, pub(crate) Arch);
 
 #[allow(clippy::len_without_is_empty)]
-impl<'a> Insn<'a> {
+impl Insn<'_> {
     /// Create an `Insn` from a raw pointer to a [`capstone_sys::cs_insn`].
     ///
     /// This function serves to allow integration with libraries which generate `capstone_sys::cs_insn`'s internally.
@@ -280,7 +280,7 @@ impl<'a> Insn<'a> {
     }
 }
 
-impl<'a> From<&Insn<'_>> for OwnedInsn<'a> {
+impl From<&Insn<'_>> for OwnedInsn<'_> {
     // SAFETY: assumes that `cs_detail` struct transitively only contains owned
     // types and no pointers, including the union over the architecture-specific
     // types.
@@ -324,7 +324,7 @@ pub struct OwnedInsn<'a> {
     pub(crate) _marker: PhantomData<&'a InsnDetail<'a>>,
 }
 
-impl<'a> Debug for Insn<'a> {
+impl Debug for Insn<'_> {
     fn fmt(&self, fmt: &mut Formatter) -> Result<(), Error> {
         fmt.debug_struct("Insn")
             .field("address", &self.address())
@@ -336,7 +336,7 @@ impl<'a> Debug for Insn<'a> {
     }
 }
 
-impl<'a> Display for Insn<'a> {
+impl Display for Insn<'_> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         write!(fmt, "{:#x}: ", self.address())?;
         if let Some(mnemonic) = self.mnemonic() {
@@ -349,27 +349,27 @@ impl<'a> Display for Insn<'a> {
     }
 }
 
-impl<'a> Drop for OwnedInsn<'a> {
+impl Drop for OwnedInsn<'_> {
     fn drop(&mut self) {
         if let Some(ptr) = core::ptr::NonNull::new(self.insn.detail) {
             unsafe { drop(Box::from_raw(ptr.as_ptr())) }
         }
     }
 }
 
-impl<'a> Debug for OwnedInsn<'a> {
+impl Debug for OwnedInsn<'_> {
     fn fmt(&self, fmt: &mut Formatter) -> Result<(), Error> {
         Debug::fmt(&self.deref(), fmt)
     }
 }
 
-impl<'a> Display for OwnedInsn<'a> {
+impl Display for OwnedInsn<'_> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         Display::fmt(&self.deref(), fmt)
     }
 }
 
-impl<'a> InsnDetail<'a> {
+impl InsnDetail<'_> {
     #[cfg(feature = "full")]
     /// Returns the implicit read registers
     pub fn regs_read(&self) -> &[RegId] {
@@ -436,7 +436,7 @@ impl<'a> InsnDetail<'a> {
 }
 
 #[cfg(feature = "full")]
-impl<'a> Debug for InsnDetail<'a> {
+impl Debug for InsnDetail<'_> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         fmt.debug_struct("Detail")
             .field("regs_read", &self.regs_read())
@@ -453,7 +453,7 @@ impl<'a> Debug for InsnDetail<'a> {
     }
 }
 
-impl<'a> Display for Instructions<'a> {
+impl Display for Instructions<'_> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         for instruction in self.iter() {
             write!(fmt, "{:x}:\t", instruction.address())?;

capstone-rs/src/test.rs

@@ -120,12 +120,12 @@ fn test_x86_names() {
             assert_eq!(cs.group_name(InsnGroupId(1)), Some(String::from("jump")));
 
             let reg_id = RegId(250);
-            if let Some(_) = cs.reg_name(reg_id) {
+            if cs.reg_name(reg_id).is_some() {
                 panic!("invalid register worked")
             }
 
             let insn_id = InsnId(6000);
-            if let Some(_) = cs.insn_name(insn_id) {
+            if cs.insn_name(insn_id).is_some() {
                 panic!("invalid instruction worked")
             }
 

capstone-sys/common.rs

@@ -12,7 +12,7 @@ pub struct CapstoneArchInfo<'a> {
     cs_name: &'a str,
 }
 
-impl<'a> CapstoneArchInfo<'a> {
+impl CapstoneArchInfo<'_> {
     /// Get the name of the C header
     pub fn header_name(&self) -> &str {
         self.header_name