Add driver for SwCc after rebase. #6565
rslawsonci.yml
on: push
Build dependencies
2m 23s
bittide-instances hardware-in-the-loop test matrix generation
22s
bittide-instances synthesis matrix generation
16s
bittide-experiments unittests
50s
Bittide tests
4m 38s
Rust Lints
28s
Firmware Support Unit Tests
2m 8s
Firmware Limit Checks
1m 13s
bittide-instances doctests
1m 28s
bittide-instances unittests
1m 46s
Matrix: synth
Matrix: HITL
All jobs finished
4s
Annotations
4 errors and 4 warnings
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HITL (swCcTopologyTest, test)
Process completed with exit code 1.
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HITL (vexRiscvTcpTest, test)
Process completed with exit code 1.
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Generate clock control report
Process completed with exit code 1.
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All jobs finished
Process completed with exit code 1.
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HITL (linkConfigurationTest, test)
No files were found with the provided path: _build/vivado/*/ila-data
_build/hitl/*. No artifacts will be uploaded.
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HITL (transceiversUpTest, test)
No files were found with the provided path: _build/vivado/*/ila-data
_build/hitl/*. No artifacts will be uploaded.
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Generate clock control report
No files were found with the provided path: reports. No artifacts will be uploaded.
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Generate clock control report
No files were found with the provided path: plot-sources. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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_build-linkConfigurationTest
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12.2 MB |
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_build-safeDffSynchronizer
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2.59 KB |
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_build-swCcTopologyTest
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278 MB |
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_build-swCcTopologyTest-debug
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8 KB |
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_build-transceiversUpTest
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12.9 MB |
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_build-vexRiscvTcpTest
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48.2 MB |
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_build-vexRiscvTcpTest-debug
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1.22 KB |
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_build-vexRiscvTest
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40.2 MB |
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_build-vexRiscvTest-debug
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202 KB |
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