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Add msl to ARMConstantTweak and recognise ldrsw to prevent delocator errors #2177

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Merged
merged 9 commits into from
Feb 11, 2025
Merged

Add msl to ARMConstantTweak and recognise ldrsw to prevent delocator errors #2177

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53dc064
add msl to ARMConstantTweak
jakemas Feb 7, 2025
c6d0748
Merge branch 'main' of github.com:jakemas/aws-lc
jakemas Feb 7, 2025
d4b6cb2
added ldrsw fix
jakemas Feb 7, 2025
538337c
learned asmb added test
jakemas Feb 8, 2025
da137bc
test msl
jakemas Feb 8, 2025
6d56652
tab not space
jakemas Feb 8, 2025
f45cf24
Merge branch 'main' into delocator-peg-msl
jakemas Feb 8, 2025
6df1307
updated out
jakemas Feb 8, 2025
b289bd6
Merge branch 'delocator-peg-msl' of github.com:jakemas/aws-lc into de…
jakemas Feb 8, 2025
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8 changes: 4 additions & 4 deletions util/fipstools/delocate/delocate.go
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Original file line number Diff line number Diff line change
Expand Up @@ -640,8 +640,8 @@ func (d *delocation) processAarch64Instruction(statement, instruction *node32) (

if parts != nil {
if parts.pegRule == ruleARMGOTLow12 {
if instructionName != "ldr" {
panic("Symbol reference outside of ldr instruction")
if instructionName != "ldr" && instructionName != "ldrsw" {
panic("Symbol reference outside of ldr/ldrsw instruction")
}

if skipWS(parts.next) != nil || parts.up.next != nil {
Expand All @@ -656,8 +656,8 @@ func (d *delocation) processAarch64Instruction(statement, instruction *node32) (
}
return statement, nil
} else if parts.pegRule == ruleLow12BitsSymbolRef {
if instructionName != "ldr" {
panic("Symbol reference outside of ldr instruction")
if instructionName != "ldr" && instructionName != "ldrsw" {
panic("Symbol reference outside of ldr/ldrsw instruction")
}

// The check for "parts.up.next != nil" was removed because gcc/release appends an
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2 changes: 1 addition & 1 deletion util/fipstools/delocate/delocate.peg
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Expand Up @@ -87,7 +87,7 @@ RegisterOrConstant <- (('%'[[A-Z]][[A-Z0-9]]*) /
('#(' [0-9]+ ')') /
ARMRegister)
![fb:(+\-]
ARMConstantTweak <- ((([us] "xt" [xwhb]) / "lsl" / "lsr" / "ror" / "asr") (WS '#'? Offset)?)/
ARMConstantTweak <- ((([us] "xt" [xwhb]) / "lsl" / "lsr" / "ror" / "asr" / "msl") (WS '#'? Offset)?)/
"mul vl" # multiply offset by the hardware's vector length
ARMRegister <- "sp" / ([xwdqshb] [0-9] [0-9]? !(ARMRegisterBoundary)) / "xzr" / "wzr" / "NZCV" / ARMVectorRegister / SVE2PredicateRegister /
('{' WS? ARMVectorRegister WS? ([,\-] WS? ARMVectorRegister)* WS? '}' ('[' [0-9] [0-9]? ']')? )
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