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[Hardware][Xilinx] explicitly specify acc dep distance to avoid hidden pitfall #8

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[Hardware][Xilinx] explicitly specify acc dep distance to avoid hidden pitfall #8

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5 changes: 5 additions & 0 deletions config/pkg_config.py
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@ class PkgConfig(object):
"LOG_INP_BUFF_SIZE",
"LOG_WGT_BUFF_SIZE",
"LOG_ACC_BUFF_SIZE",
"ACC_DEP_DISTANCE",
]

def __init__(self, cfg):
Expand All @@ -73,6 +74,10 @@ def __init__(self, cfg):
cfg["LOG_OUT_WIDTH"] -
cfg["LOG_ACC_WIDTH"])

# export VTA_ACC_DEP_DISTANCE env so that VTA runtime can use it to VerifyDep
if "ACC_DEP_DISTANCE" in cfg:
os.environ['VTA_ACC_DEP_DISTANCE'] = str(cfg['ACC_DEP_DISTANCE'])

# Update cfg now that we've extended it
self.__dict__.update(cfg)

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3 changes: 2 additions & 1 deletion config/vta_config.json
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Original file line number Diff line number Diff line change
Expand Up @@ -9,5 +9,6 @@
"LOG_UOP_BUFF_SIZE" : 15,
"LOG_INP_BUFF_SIZE" : 15,
"LOG_WGT_BUFF_SIZE" : 18,
"LOG_ACC_BUFF_SIZE" : 17
"LOG_ACC_BUFF_SIZE" : 17,
"ACC_DEP_DISTANCE" : 3
}
4 changes: 4 additions & 0 deletions hardware/xilinx/src/vta.cc
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Expand Up @@ -447,7 +447,11 @@ PRAGMA_HLS(HLS INTERFACE s_axilite port = done bundle = CONTROL_BUS offset = VTA
static bus_T acc_mem[VTA_ACC_BUFF_DEPTH][ACC_MAT_AXI_RATIO];
#pragma HLS ARRAY_RESHAPE variable = acc_mem complete dim=2
// This is necessary to obtain II=1
#ifdef VTA_ACC_DEP_DISTANCE
#pragma HLS DEPENDENCE variable = acc_mem inter distance=VTA_ACC_DEP_DISTANCE true
#else
#pragma HLS DEPENDENCE variable = acc_mem inter false
#endif

// Pop GEMM instruction
insn_T raw_insn = gemm_queue.read();
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