Skip to content

arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing #18501

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
jasonbu wants to merge 7 commits into
base: master
Choose a base branch
from
+1,326 −26
Open

arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing #18501

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
7 commits
Select commit Hold shift + click to select a range
be6481f
cmake: arm64/common sync modifyreg sources with Make.defs
jasonbu Mar 6, 2026
0ccbefd
mmcsd: fix MMC bus width switch using wrong condition and add 8-bit s…
jasonbu Mar 6, 2026
e14b890
imx9: imx95 fix uSDHC IRQ naming to match NuttX USDHC convention
jasonbu Mar 6, 2026
f63c81e
imx9: add GPIO support for imx95
jasonbu Mar 6, 2026
a4e239d
imx95-a55-evk: add USDHC eMMC driver support
jasonbu Mar 6, 2026
445b79b
imx9: usdhc fix dmapreflight rejecting small unaligned buffers
jasonbu Mar 6, 2026
f594d5e
imx95-a55-evk: add MBR/GPT partition table parsing on eMMC
jasonbu Mar 6, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions arch/arm/include/imx9/imx95_irq.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -110,8 +110,8 @@
#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXTINT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXTINT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXTINT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 90) /* NOCMIX TRDC transfer error interrupt */
Expand Down Expand Up @@ -215,7 +215,7 @@
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 188) /* PDM interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 189) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 190) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 192) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXTINT + 193) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 194) /* CM33 MCM interrupt */
Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/include/imx9/imx95_irq.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -109,8 +109,8 @@
#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXT + 90) /* NOCMIX TRDC transfer error interrupt */
Expand Down Expand Up @@ -214,7 +214,7 @@
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXT + 188) /* PDM interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXT + 189) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXT + 190) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXT + 192) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXT + 193) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXT + 194) /* CM33 MCM interrupt */
Expand Down
1 change: 1 addition & 0 deletions arch/arm64/src/common/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ list(APPEND SRCS arm64_perf.c arm64_tcbinfo.c)
list(APPEND SRCS arm64_arch_timer.c arm64_cache.c)
list(APPEND SRCS arm64_doirq.c arm64_fatal.c)
list(APPEND SRCS arm64_syscall.c)
list(APPEND SRCS arm64_modifyreg8.c arm64_modifyreg16.c arm64_modifyreg32.c)

# Use common heap allocation for now (may need to be customized later)
list(APPEND SRCS arm64_allocateheap.c)
Expand Down
4 changes: 3 additions & 1 deletion arch/arm64/src/imx9/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,9 @@ set(SRCS imx9_boot.c imx9_clockconfig.c imx9_iomuxc.c imx9_lpuart.c
imx9_lowputc.c)

if(CONFIG_ARCH_CHIP_IMX93)
list(APPEND SRCS imx9_ccm.c imx9_gpio.c)
list(APPEND SRCS imx9_ccm.c imx9_gpio.c imx9_gpiobase.c)
elseif(CONFIG_ARCH_CHIP_IMX95)
list(APPEND SRCS imx9_gpio.c imx9_gpiobase.c)
endif()

if(CONFIG_IMX9_GPIO_IRQ)
Expand Down
3 changes: 3 additions & 0 deletions arch/arm64/src/imx9/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -202,6 +202,9 @@ choice
depends on IMX9_USDHC2
prompt "Bus width for USDHC2"
default IMX9_USDHC2_WIDTH_D1_D4
---help---
USDHC2 supports up to 4-bit data width only according to chip
spec. No 8-bit option is provided.

config IMX9_USDHC2_WIDTH_D1_ONLY
bool "One bit"
Expand Down
4 changes: 3 additions & 1 deletion arch/arm64/src/imx9/Make.defs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,9 @@ endif
CHIP_CSRCS = imx9_boot.c

ifeq ($(CONFIG_ARCH_CHIP_IMX93),y)
CHIP_CSRCS += imx9_ccm.c imx9_gpio.c
CHIP_CSRCS += imx9_ccm.c imx9_gpio.c imx9_gpiobase.c
else ifeq ($(CONFIG_ARCH_CHIP_IMX95),y)
CHIP_CSRCS += imx9_gpio.c imx9_gpiobase.c
endif

CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c imx9_clockconfig.c
Expand Down
Loading
Loading