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sched/spinlock: Replace critical_section with spinlock. #18270

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sched/spinlock: Replace critical_section with spinlock. #18270

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@wangzhi16 wangzhi16 commented Jan 30, 2026 •
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Summary

This PR aggregates three closely related architecture-level changes that optimize critical-section handling on various ARM platforms by replacing broad critical-section locks with more targeted spinlocks or mutexes. The goal is to clarify locking responsibilities, reduce contention, and improve system responsiveness.

Included Commits

  • b4f7a03 — arm64/common: Critical Section Optimization. — wangzhi16 (2025-06-20)

    • Replace broad critical_section usage with spinlocks to protect distinct resources.

  • 23f98ce — arm/phy62xx: Critical Section Optimization. — wangzhi16 (2025-06-20)

    • Narrow critical-section scope by using more appropriate synchronization primitives (spinlocks) in PHY62xx code.

  • 90be4bc — arm/rtl8720c: Critical Section Optimization. — wangzhi16 (2025-06-20)

    • Replace critical_section with spinlock or mutex where appropriate in RTL8720C driver code.

Rationale

  • Replacing coarse-grained critical_section usage with per-resource spinlocks/mutexes:
    • Clarifies which resource each lock protects, improving maintainability.
    • Reduces contention and blocking time for unrelated subsystems, improving responsiveness.
    • Enables finer-grained concurrency and potential performance benefits on multicore or high-interrupt-rate systems.

Impact

  • Functional: No intended change to higher-level behavior; synchronization semantics should remain correct while reducing unnecessary blocking. Care must be taken to preserve lock ordering where multiple locks are acquired to avoid deadlocks.
  • Performance: Expected reduction in contention and improved system responsiveness, particularly under high concurrency or interrupt load.
  • Compatibility: Source-level changes; should compile normally. Reviewers should verify there are no subtle ordering or memory visibility regressions introduced by replacing enter_critical_section/leave_critical_section with spinlocks/mutexes.

Testing

  1. Build validation
./tools/configure.sh -l amrv7a:smp
make -j$(nproc)
  1. Functional tests
ostest

PASS

@wangzhi16
arm/rtl8720c: Critical Section Optimization.
90be4bc 
Replace critical_section with spinlock or mutex.
The benefits of doing this are:

1. It makes the code logic clearer, with different resources protected by different locks.

2. It improves system responsiveness and avoids contention issues caused by acquiring the same large lock.

Signed-off-by: wangzhi16 <[email protected]>
@wangzhi16
arm/phy62xx: Critical Section Optimization.
23f98ce 
The benefits of doing this are:

1. It makes the code logic clearer, with different resources protected by different locks.

2. It improves system responsiveness and avoids contention issues caused by acquiring the same large lock.

Signed-off-by: wangzhi16 <[email protected]>
@wangzhi16
arm64/common: Critical Section Optimization.
b4f7a03 
Replace critical_section with spinlock.
The benefits of doing this are:

1. It makes the code logic clearer, with different resources protected by different locks.

2. It improves system responsiveness and avoids contention issues caused by acquiring the same large lock.

Signed-off-by: wangzhi16 <[email protected]>
@github-actions github-actions bot added Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Size: M The size of the change in this PR is medium labels Jan 30, 2026
@wangzhi16
arch/xtensa: replace critical_section with spinlock.
661a829 
The benefits of doing this are:

1. It makes the code logic clearer, with different resources protected by different locks.

2. It improves system responsiveness and avoids contention issues caused by acquiring the same large lock.

Signed-off-by: wangzhi16 <[email protected]>
@github-actions github-actions bot added the Arch: xtensa Issues related to the Xtensa architecture label Jan 30, 2026
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@pussuw pussuw Awaiting requested review from pussuw pussuw is a code owner

@xiaoxiang781216 xiaoxiang781216 Awaiting requested review from xiaoxiang781216 xiaoxiang781216 is a code owner

@pkarashchenko pkarashchenko Awaiting requested review from pkarashchenko pkarashchenko is a code owner

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Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: xtensa Issues related to the Xtensa architecture Size: M The size of the change in this PR is medium

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